Alison Wang c207ff6129 arm: ls102xa: Remove bit reversing for SCFG registers ... SCFG_SCFGREVCR is SCFG bit reverse register. This register must be written with 0xFFFFFFFF before writing to any other SCFG register. Then other SCFG register could be written in big-endian mode. Address: 157_0000h base + 200h offset = 157_0200h Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15|16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 W/R SCFGREV Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0-31 SCFGREV SCFG Bit Reverse Control Filed 32'h 0000_0000 - No bit reverse is applied 32'h FFFF_FFFF - Bit reverse is applied; so 31:0 will be stored/read as 0:31 This patch removes the bit reversing for SCFG registers in u-boot. It will be implemented through PBI commands in RCW .pbi write 0x570200, 0xffffffff .end So other SCFG register could be written in big-endian mode in u-boot or kernel directly. Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>		2014-11-24 09:27:23 -08:00
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clock.h	arm: ls102xa: Add Freescale LS102xA SoC support	2014-09-08 10:30:32 -07:00
config.h	drivers: usb: fsl: Define USB configs for LS102XA	2014-11-24 09:27:22 -08:00
fsl_serdes.h	arm: ls102xa: Add Freescale LS102xA SoC support	2014-09-08 10:30:32 -07:00
immap_ls102xa.h	arm: ls102xa: Remove bit reversing for SCFG registers	2014-11-24 09:27:23 -08:00
imx-regs.h	arm: ls102xa: Add Freescale LS102xA SoC support	2014-09-08 10:30:32 -07:00