mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-18 18:59:44 +00:00
1fd92db83d
Update the naming convention used in the network stack functions and variables that Ethernet drivers use to interact with it. This cleans up the temporary hacks that were added to this interface along with the DM support. This patch has a few remaining checkpatch.pl failures that would be out of the scope of this patch to fix (drivers that are in gross violation of checkpatch.pl). Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> Acked-by: Simon Glass <sjg@chromium.org>
763 lines
20 KiB
C
763 lines
20 KiB
C
/*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <malloc.h>
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#include <net.h>
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#include <netdev.h>
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#include <pci.h>
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#undef DEBUG_SROM
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#undef DEBUG_SROM2
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#undef UPDATE_SROM
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/* PCI Registers.
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*/
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#define PCI_CFDA_PSM 0x43
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#define CFRV_RN 0x000000f0 /* Revision Number */
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#define WAKEUP 0x00 /* Power Saving Wakeup */
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#define SLEEP 0x80 /* Power Saving Sleep Mode */
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#define DC2114x_BRK 0x0020 /* CFRV break between DC21142 & DC21143 */
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/* Ethernet chip registers.
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*/
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#define DE4X5_BMR 0x000 /* Bus Mode Register */
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#define DE4X5_TPD 0x008 /* Transmit Poll Demand Reg */
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#define DE4X5_RRBA 0x018 /* RX Ring Base Address Reg */
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#define DE4X5_TRBA 0x020 /* TX Ring Base Address Reg */
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#define DE4X5_STS 0x028 /* Status Register */
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#define DE4X5_OMR 0x030 /* Operation Mode Register */
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#define DE4X5_SICR 0x068 /* SIA Connectivity Register */
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#define DE4X5_APROM 0x048 /* Ethernet Address PROM */
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/* Register bits.
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*/
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#define BMR_SWR 0x00000001 /* Software Reset */
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#define STS_TS 0x00700000 /* Transmit Process State */
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#define STS_RS 0x000e0000 /* Receive Process State */
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#define OMR_ST 0x00002000 /* Start/Stop Transmission Command */
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#define OMR_SR 0x00000002 /* Start/Stop Receive */
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#define OMR_PS 0x00040000 /* Port Select */
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#define OMR_SDP 0x02000000 /* SD Polarity - MUST BE ASSERTED */
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#define OMR_PM 0x00000080 /* Pass All Multicast */
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/* Descriptor bits.
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*/
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#define R_OWN 0x80000000 /* Own Bit */
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#define RD_RER 0x02000000 /* Receive End Of Ring */
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#define RD_LS 0x00000100 /* Last Descriptor */
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#define RD_ES 0x00008000 /* Error Summary */
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#define TD_TER 0x02000000 /* Transmit End Of Ring */
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#define T_OWN 0x80000000 /* Own Bit */
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#define TD_LS 0x40000000 /* Last Segment */
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#define TD_FS 0x20000000 /* First Segment */
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#define TD_ES 0x00008000 /* Error Summary */
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#define TD_SET 0x08000000 /* Setup Packet */
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/* The EEPROM commands include the alway-set leading bit. */
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#define SROM_WRITE_CMD 5
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#define SROM_READ_CMD 6
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#define SROM_ERASE_CMD 7
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#define SROM_HWADD 0x0014 /* Hardware Address offset in SROM */
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#define SROM_RD 0x00004000 /* Read from Boot ROM */
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#define EE_DATA_WRITE 0x04 /* EEPROM chip data in. */
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#define EE_WRITE_0 0x4801
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#define EE_WRITE_1 0x4805
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#define EE_DATA_READ 0x08 /* EEPROM chip data out. */
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#define SROM_SR 0x00000800 /* Select Serial ROM when set */
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#define DT_IN 0x00000004 /* Serial Data In */
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#define DT_CLK 0x00000002 /* Serial ROM Clock */
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#define DT_CS 0x00000001 /* Serial ROM Chip Select */
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#define POLL_DEMAND 1
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#ifdef CONFIG_TULIP_FIX_DAVICOM
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#define RESET_DM9102(dev) {\
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unsigned long i;\
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i=INL(dev, 0x0);\
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udelay(1000);\
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OUTL(dev, i | BMR_SWR, DE4X5_BMR);\
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udelay(1000);\
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}
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#else
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#define RESET_DE4X5(dev) {\
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int i;\
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i=INL(dev, DE4X5_BMR);\
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udelay(1000);\
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OUTL(dev, i | BMR_SWR, DE4X5_BMR);\
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udelay(1000);\
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OUTL(dev, i, DE4X5_BMR);\
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udelay(1000);\
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for (i=0;i<5;i++) {INL(dev, DE4X5_BMR); udelay(10000);}\
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udelay(1000);\
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}
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#endif
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#define START_DE4X5(dev) {\
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s32 omr; \
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omr = INL(dev, DE4X5_OMR);\
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omr |= OMR_ST | OMR_SR;\
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OUTL(dev, omr, DE4X5_OMR); /* Enable the TX and/or RX */\
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}
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#define STOP_DE4X5(dev) {\
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s32 omr; \
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omr = INL(dev, DE4X5_OMR);\
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omr &= ~(OMR_ST|OMR_SR);\
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OUTL(dev, omr, DE4X5_OMR); /* Disable the TX and/or RX */ \
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}
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#define NUM_RX_DESC PKTBUFSRX
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#ifndef CONFIG_TULIP_FIX_DAVICOM
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#define NUM_TX_DESC 1 /* Number of TX descriptors */
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#else
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#define NUM_TX_DESC 4
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#endif
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#define RX_BUFF_SZ PKTSIZE_ALIGN
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#define TOUT_LOOP 1000000
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#define SETUP_FRAME_LEN 192
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#define ETH_ALEN 6
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struct de4x5_desc {
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volatile s32 status;
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u32 des1;
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u32 buf;
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u32 next;
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};
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static struct de4x5_desc rx_ring[NUM_RX_DESC] __attribute__ ((aligned(32))); /* RX descriptor ring */
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static struct de4x5_desc tx_ring[NUM_TX_DESC] __attribute__ ((aligned(32))); /* TX descriptor ring */
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static int rx_new; /* RX descriptor ring pointer */
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static int tx_new; /* TX descriptor ring pointer */
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static char rxRingSize;
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static char txRingSize;
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#if defined(UPDATE_SROM) || !defined(CONFIG_TULIP_FIX_DAVICOM)
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static void sendto_srom(struct eth_device* dev, u_int command, u_long addr);
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static int getfrom_srom(struct eth_device* dev, u_long addr);
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static int do_eeprom_cmd(struct eth_device *dev, u_long ioaddr,int cmd,int cmd_len);
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static int do_read_eeprom(struct eth_device *dev,u_long ioaddr,int location,int addr_len);
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#endif /* UPDATE_SROM || !CONFIG_TULIP_FIX_DAVICOM */
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#ifdef UPDATE_SROM
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static int write_srom(struct eth_device *dev, u_long ioaddr, int index, int new_value);
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static void update_srom(struct eth_device *dev, bd_t *bis);
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#endif
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#ifndef CONFIG_TULIP_FIX_DAVICOM
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static int read_srom(struct eth_device *dev, u_long ioaddr, int index);
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static void read_hw_addr(struct eth_device* dev, bd_t * bis);
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#endif /* CONFIG_TULIP_FIX_DAVICOM */
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static void send_setup_frame(struct eth_device* dev, bd_t * bis);
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static int dc21x4x_init(struct eth_device* dev, bd_t* bis);
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static int dc21x4x_send(struct eth_device *dev, void *packet, int length);
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static int dc21x4x_recv(struct eth_device* dev);
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static void dc21x4x_halt(struct eth_device* dev);
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#ifdef CONFIG_TULIP_SELECT_MEDIA
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extern void dc21x4x_select_media(struct eth_device* dev);
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#endif
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#if defined(CONFIG_E500)
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#define phys_to_bus(a) (a)
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#else
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#define phys_to_bus(a) pci_phys_to_mem((pci_dev_t)dev->priv, a)
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#endif
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static int INL(struct eth_device* dev, u_long addr)
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{
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return le32_to_cpu(*(volatile u_long *)(addr + dev->iobase));
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}
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static void OUTL(struct eth_device* dev, int command, u_long addr)
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{
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*(volatile u_long *)(addr + dev->iobase) = cpu_to_le32(command);
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}
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static struct pci_device_id supported[] = {
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{ PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_TULIP_FAST },
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{ PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21142 },
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#ifdef CONFIG_TULIP_FIX_DAVICOM
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{ PCI_VENDOR_ID_DAVICOM, PCI_DEVICE_ID_DAVICOM_DM9102A },
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#endif
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{ }
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};
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int dc21x4x_initialize(bd_t *bis)
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{
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int idx=0;
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int card_number = 0;
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unsigned int cfrv;
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unsigned char timer;
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pci_dev_t devbusfn;
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unsigned int iobase;
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unsigned short status;
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struct eth_device* dev;
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while(1) {
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devbusfn = pci_find_devices(supported, idx++);
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if (devbusfn == -1) {
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break;
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}
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/* Get the chip configuration revision register. */
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pci_read_config_dword(devbusfn, PCI_REVISION_ID, &cfrv);
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#ifndef CONFIG_TULIP_FIX_DAVICOM
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if ((cfrv & CFRV_RN) < DC2114x_BRK ) {
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printf("Error: The chip is not DC21143.\n");
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continue;
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}
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#endif
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pci_read_config_word(devbusfn, PCI_COMMAND, &status);
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status |=
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#ifdef CONFIG_TULIP_USE_IO
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PCI_COMMAND_IO |
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#else
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PCI_COMMAND_MEMORY |
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#endif
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PCI_COMMAND_MASTER;
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pci_write_config_word(devbusfn, PCI_COMMAND, status);
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pci_read_config_word(devbusfn, PCI_COMMAND, &status);
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#ifdef CONFIG_TULIP_USE_IO
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if (!(status & PCI_COMMAND_IO)) {
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printf("Error: Can not enable I/O access.\n");
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continue;
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}
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#else
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if (!(status & PCI_COMMAND_MEMORY)) {
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printf("Error: Can not enable MEMORY access.\n");
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continue;
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}
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#endif
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if (!(status & PCI_COMMAND_MASTER)) {
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printf("Error: Can not enable Bus Mastering.\n");
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continue;
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}
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/* Check the latency timer for values >= 0x60. */
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pci_read_config_byte(devbusfn, PCI_LATENCY_TIMER, &timer);
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if (timer < 0x60) {
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pci_write_config_byte(devbusfn, PCI_LATENCY_TIMER, 0x60);
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}
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#ifdef CONFIG_TULIP_USE_IO
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/* read BAR for memory space access */
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pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, &iobase);
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iobase &= PCI_BASE_ADDRESS_IO_MASK;
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#else
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/* read BAR for memory space access */
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pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_1, &iobase);
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iobase &= PCI_BASE_ADDRESS_MEM_MASK;
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#endif
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debug ("dc21x4x: DEC 21142 PCI Device @0x%x\n", iobase);
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dev = (struct eth_device*) malloc(sizeof *dev);
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if (!dev) {
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printf("Can not allocalte memory of dc21x4x\n");
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break;
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}
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memset(dev, 0, sizeof(*dev));
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#ifdef CONFIG_TULIP_FIX_DAVICOM
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sprintf(dev->name, "Davicom#%d", card_number);
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#else
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sprintf(dev->name, "dc21x4x#%d", card_number);
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#endif
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#ifdef CONFIG_TULIP_USE_IO
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dev->iobase = pci_io_to_phys(devbusfn, iobase);
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#else
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dev->iobase = pci_mem_to_phys(devbusfn, iobase);
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#endif
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dev->priv = (void*) devbusfn;
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dev->init = dc21x4x_init;
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dev->halt = dc21x4x_halt;
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dev->send = dc21x4x_send;
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dev->recv = dc21x4x_recv;
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/* Ensure we're not sleeping. */
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pci_write_config_byte(devbusfn, PCI_CFDA_PSM, WAKEUP);
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udelay(10 * 1000);
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#ifndef CONFIG_TULIP_FIX_DAVICOM
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read_hw_addr(dev, bis);
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#endif
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eth_register(dev);
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card_number++;
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}
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return card_number;
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}
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static int dc21x4x_init(struct eth_device* dev, bd_t* bis)
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{
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int i;
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int devbusfn = (int) dev->priv;
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/* Ensure we're not sleeping. */
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pci_write_config_byte(devbusfn, PCI_CFDA_PSM, WAKEUP);
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#ifdef CONFIG_TULIP_FIX_DAVICOM
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RESET_DM9102(dev);
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#else
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RESET_DE4X5(dev);
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#endif
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if ((INL(dev, DE4X5_STS) & (STS_TS | STS_RS)) != 0) {
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printf("Error: Cannot reset ethernet controller.\n");
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return -1;
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}
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#ifdef CONFIG_TULIP_SELECT_MEDIA
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dc21x4x_select_media(dev);
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#else
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OUTL(dev, OMR_SDP | OMR_PS | OMR_PM, DE4X5_OMR);
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#endif
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for (i = 0; i < NUM_RX_DESC; i++) {
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rx_ring[i].status = cpu_to_le32(R_OWN);
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rx_ring[i].des1 = cpu_to_le32(RX_BUFF_SZ);
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rx_ring[i].buf = cpu_to_le32(
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phys_to_bus((u32)net_rx_packets[i]));
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#ifdef CONFIG_TULIP_FIX_DAVICOM
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rx_ring[i].next = cpu_to_le32(
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phys_to_bus((u32)&rx_ring[(i + 1) % NUM_RX_DESC]));
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#else
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rx_ring[i].next = 0;
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#endif
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}
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for (i=0; i < NUM_TX_DESC; i++) {
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tx_ring[i].status = 0;
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tx_ring[i].des1 = 0;
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tx_ring[i].buf = 0;
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#ifdef CONFIG_TULIP_FIX_DAVICOM
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tx_ring[i].next = cpu_to_le32(phys_to_bus((u32) &tx_ring[(i+1) % NUM_TX_DESC]));
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#else
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tx_ring[i].next = 0;
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#endif
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}
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rxRingSize = NUM_RX_DESC;
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txRingSize = NUM_TX_DESC;
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/* Write the end of list marker to the descriptor lists. */
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rx_ring[rxRingSize - 1].des1 |= cpu_to_le32(RD_RER);
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tx_ring[txRingSize - 1].des1 |= cpu_to_le32(TD_TER);
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/* Tell the adapter where the TX/RX rings are located. */
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OUTL(dev, phys_to_bus((u32) &rx_ring), DE4X5_RRBA);
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OUTL(dev, phys_to_bus((u32) &tx_ring), DE4X5_TRBA);
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START_DE4X5(dev);
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tx_new = 0;
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rx_new = 0;
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send_setup_frame(dev, bis);
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return 0;
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}
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static int dc21x4x_send(struct eth_device *dev, void *packet, int length)
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{
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int status = -1;
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int i;
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if (length <= 0) {
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printf("%s: bad packet size: %d\n", dev->name, length);
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goto Done;
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}
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for(i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) {
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if (i >= TOUT_LOOP) {
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printf("%s: tx error buffer not ready\n", dev->name);
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goto Done;
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}
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}
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tx_ring[tx_new].buf = cpu_to_le32(phys_to_bus((u32) packet));
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tx_ring[tx_new].des1 = cpu_to_le32(TD_TER | TD_LS | TD_FS | length);
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tx_ring[tx_new].status = cpu_to_le32(T_OWN);
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OUTL(dev, POLL_DEMAND, DE4X5_TPD);
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for(i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) {
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if (i >= TOUT_LOOP) {
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printf(".%s: tx buffer not ready\n", dev->name);
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goto Done;
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}
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}
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if (le32_to_cpu(tx_ring[tx_new].status) & TD_ES) {
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#if 0 /* test-only */
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printf("TX error status = 0x%08X\n",
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le32_to_cpu(tx_ring[tx_new].status));
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#endif
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tx_ring[tx_new].status = 0x0;
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goto Done;
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}
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status = length;
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Done:
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tx_new = (tx_new+1) % NUM_TX_DESC;
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return status;
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}
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static int dc21x4x_recv(struct eth_device* dev)
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{
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s32 status;
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int length = 0;
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for ( ; ; ) {
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status = (s32)le32_to_cpu(rx_ring[rx_new].status);
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if (status & R_OWN) {
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break;
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}
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if (status & RD_LS) {
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/* Valid frame status.
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*/
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if (status & RD_ES) {
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/* There was an error.
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*/
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printf("RX error status = 0x%08X\n", status);
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} else {
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/* A valid frame received.
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*/
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length = (le32_to_cpu(rx_ring[rx_new].status) >> 16);
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/* Pass the packet up to the protocol
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* layers.
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*/
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net_process_received_packet(
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net_rx_packets[rx_new], length - 4);
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}
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/* Change buffer ownership for this frame, back
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* to the adapter.
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*/
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rx_ring[rx_new].status = cpu_to_le32(R_OWN);
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}
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/* Update entry information.
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*/
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rx_new = (rx_new + 1) % rxRingSize;
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}
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return length;
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}
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static void dc21x4x_halt(struct eth_device* dev)
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{
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int devbusfn = (int) dev->priv;
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STOP_DE4X5(dev);
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OUTL(dev, 0, DE4X5_SICR);
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pci_write_config_byte(devbusfn, PCI_CFDA_PSM, SLEEP);
|
|
}
|
|
|
|
static void send_setup_frame(struct eth_device* dev, bd_t *bis)
|
|
{
|
|
int i;
|
|
char setup_frame[SETUP_FRAME_LEN];
|
|
char *pa = &setup_frame[0];
|
|
|
|
memset(pa, 0xff, SETUP_FRAME_LEN);
|
|
|
|
for (i = 0; i < ETH_ALEN; i++) {
|
|
*(pa + (i & 1)) = dev->enetaddr[i];
|
|
if (i & 0x01) {
|
|
pa += 4;
|
|
}
|
|
}
|
|
|
|
for(i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) {
|
|
if (i >= TOUT_LOOP) {
|
|
printf("%s: tx error buffer not ready\n", dev->name);
|
|
goto Done;
|
|
}
|
|
}
|
|
|
|
tx_ring[tx_new].buf = cpu_to_le32(phys_to_bus((u32) &setup_frame[0]));
|
|
tx_ring[tx_new].des1 = cpu_to_le32(TD_TER | TD_SET| SETUP_FRAME_LEN);
|
|
tx_ring[tx_new].status = cpu_to_le32(T_OWN);
|
|
|
|
OUTL(dev, POLL_DEMAND, DE4X5_TPD);
|
|
|
|
for(i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) {
|
|
if (i >= TOUT_LOOP) {
|
|
printf("%s: tx buffer not ready\n", dev->name);
|
|
goto Done;
|
|
}
|
|
}
|
|
|
|
if (le32_to_cpu(tx_ring[tx_new].status) != 0x7FFFFFFF) {
|
|
printf("TX error status2 = 0x%08X\n", le32_to_cpu(tx_ring[tx_new].status));
|
|
}
|
|
tx_new = (tx_new+1) % NUM_TX_DESC;
|
|
|
|
Done:
|
|
return;
|
|
}
|
|
|
|
#if defined(UPDATE_SROM) || !defined(CONFIG_TULIP_FIX_DAVICOM)
|
|
/* SROM Read and write routines.
|
|
*/
|
|
static void
|
|
sendto_srom(struct eth_device* dev, u_int command, u_long addr)
|
|
{
|
|
OUTL(dev, command, addr);
|
|
udelay(1);
|
|
}
|
|
|
|
static int
|
|
getfrom_srom(struct eth_device* dev, u_long addr)
|
|
{
|
|
s32 tmp;
|
|
|
|
tmp = INL(dev, addr);
|
|
udelay(1);
|
|
|
|
return tmp;
|
|
}
|
|
|
|
/* Note: this routine returns extra data bits for size detection. */
|
|
static int do_read_eeprom(struct eth_device *dev, u_long ioaddr, int location, int addr_len)
|
|
{
|
|
int i;
|
|
unsigned retval = 0;
|
|
int read_cmd = location | (SROM_READ_CMD << addr_len);
|
|
|
|
sendto_srom(dev, SROM_RD | SROM_SR, ioaddr);
|
|
sendto_srom(dev, SROM_RD | SROM_SR | DT_CS, ioaddr);
|
|
|
|
#ifdef DEBUG_SROM
|
|
printf(" EEPROM read at %d ", location);
|
|
#endif
|
|
|
|
/* Shift the read command bits out. */
|
|
for (i = 4 + addr_len; i >= 0; i--) {
|
|
short dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
|
|
sendto_srom(dev, SROM_RD | SROM_SR | DT_CS | dataval, ioaddr);
|
|
udelay(10);
|
|
sendto_srom(dev, SROM_RD | SROM_SR | DT_CS | dataval | DT_CLK, ioaddr);
|
|
udelay(10);
|
|
#ifdef DEBUG_SROM2
|
|
printf("%X", getfrom_srom(dev, ioaddr) & 15);
|
|
#endif
|
|
retval = (retval << 1) | ((getfrom_srom(dev, ioaddr) & EE_DATA_READ) ? 1 : 0);
|
|
}
|
|
|
|
sendto_srom(dev, SROM_RD | SROM_SR | DT_CS, ioaddr);
|
|
|
|
#ifdef DEBUG_SROM2
|
|
printf(" :%X:", getfrom_srom(dev, ioaddr) & 15);
|
|
#endif
|
|
|
|
for (i = 16; i > 0; i--) {
|
|
sendto_srom(dev, SROM_RD | SROM_SR | DT_CS | DT_CLK, ioaddr);
|
|
udelay(10);
|
|
#ifdef DEBUG_SROM2
|
|
printf("%X", getfrom_srom(dev, ioaddr) & 15);
|
|
#endif
|
|
retval = (retval << 1) | ((getfrom_srom(dev, ioaddr) & EE_DATA_READ) ? 1 : 0);
|
|
sendto_srom(dev, SROM_RD | SROM_SR | DT_CS, ioaddr);
|
|
udelay(10);
|
|
}
|
|
|
|
/* Terminate the EEPROM access. */
|
|
sendto_srom(dev, SROM_RD | SROM_SR, ioaddr);
|
|
|
|
#ifdef DEBUG_SROM2
|
|
printf(" EEPROM value at %d is %5.5x.\n", location, retval);
|
|
#endif
|
|
|
|
return retval;
|
|
}
|
|
#endif /* UPDATE_SROM || !CONFIG_TULIP_FIX_DAVICOM */
|
|
|
|
/* This executes a generic EEPROM command, typically a write or write
|
|
* enable. It returns the data output from the EEPROM, and thus may
|
|
* also be used for reads.
|
|
*/
|
|
#if defined(UPDATE_SROM) || !defined(CONFIG_TULIP_FIX_DAVICOM)
|
|
static int do_eeprom_cmd(struct eth_device *dev, u_long ioaddr, int cmd, int cmd_len)
|
|
{
|
|
unsigned retval = 0;
|
|
|
|
#ifdef DEBUG_SROM
|
|
printf(" EEPROM op 0x%x: ", cmd);
|
|
#endif
|
|
|
|
sendto_srom(dev,SROM_RD | SROM_SR | DT_CS | DT_CLK, ioaddr);
|
|
|
|
/* Shift the command bits out. */
|
|
do {
|
|
short dataval = (cmd & (1 << cmd_len)) ? EE_WRITE_1 : EE_WRITE_0;
|
|
sendto_srom(dev,dataval, ioaddr);
|
|
udelay(10);
|
|
|
|
#ifdef DEBUG_SROM2
|
|
printf("%X", getfrom_srom(dev,ioaddr) & 15);
|
|
#endif
|
|
|
|
sendto_srom(dev,dataval | DT_CLK, ioaddr);
|
|
udelay(10);
|
|
retval = (retval << 1) | ((getfrom_srom(dev,ioaddr) & EE_DATA_READ) ? 1 : 0);
|
|
} while (--cmd_len >= 0);
|
|
sendto_srom(dev,SROM_RD | SROM_SR | DT_CS, ioaddr);
|
|
|
|
/* Terminate the EEPROM access. */
|
|
sendto_srom(dev,SROM_RD | SROM_SR, ioaddr);
|
|
|
|
#ifdef DEBUG_SROM
|
|
printf(" EEPROM result is 0x%5.5x.\n", retval);
|
|
#endif
|
|
|
|
return retval;
|
|
}
|
|
#endif /* UPDATE_SROM || !CONFIG_TULIP_FIX_DAVICOM */
|
|
|
|
#ifndef CONFIG_TULIP_FIX_DAVICOM
|
|
static int read_srom(struct eth_device *dev, u_long ioaddr, int index)
|
|
{
|
|
int ee_addr_size = do_read_eeprom(dev, ioaddr, 0xff, 8) & 0x40000 ? 8 : 6;
|
|
|
|
return do_eeprom_cmd(dev, ioaddr,
|
|
(((SROM_READ_CMD << ee_addr_size) | index) << 16)
|
|
| 0xffff, 3 + ee_addr_size + 16);
|
|
}
|
|
#endif /* CONFIG_TULIP_FIX_DAVICOM */
|
|
|
|
#ifdef UPDATE_SROM
|
|
static int write_srom(struct eth_device *dev, u_long ioaddr, int index, int new_value)
|
|
{
|
|
int ee_addr_size = do_read_eeprom(dev, ioaddr, 0xff, 8) & 0x40000 ? 8 : 6;
|
|
int i;
|
|
unsigned short newval;
|
|
|
|
udelay(10*1000); /* test-only */
|
|
|
|
#ifdef DEBUG_SROM
|
|
printf("ee_addr_size=%d.\n", ee_addr_size);
|
|
printf("Writing new entry 0x%4.4x to offset %d.\n", new_value, index);
|
|
#endif
|
|
|
|
/* Enable programming modes. */
|
|
do_eeprom_cmd(dev, ioaddr, (0x4f << (ee_addr_size-4)), 3+ee_addr_size);
|
|
|
|
/* Do the actual write. */
|
|
do_eeprom_cmd(dev, ioaddr,
|
|
(((SROM_WRITE_CMD<<ee_addr_size)|index) << 16) | new_value,
|
|
3 + ee_addr_size + 16);
|
|
|
|
/* Poll for write finished. */
|
|
sendto_srom(dev, SROM_RD | SROM_SR | DT_CS, ioaddr);
|
|
for (i = 0; i < 10000; i++) /* Typical 2000 ticks */
|
|
if (getfrom_srom(dev, ioaddr) & EE_DATA_READ)
|
|
break;
|
|
|
|
#ifdef DEBUG_SROM
|
|
printf(" Write finished after %d ticks.\n", i);
|
|
#endif
|
|
|
|
/* Disable programming. */
|
|
do_eeprom_cmd(dev, ioaddr, (0x40 << (ee_addr_size-4)), 3 + ee_addr_size);
|
|
|
|
/* And read the result. */
|
|
newval = do_eeprom_cmd(dev, ioaddr,
|
|
(((SROM_READ_CMD<<ee_addr_size)|index) << 16)
|
|
| 0xffff, 3 + ee_addr_size + 16);
|
|
#ifdef DEBUG_SROM
|
|
printf(" New value at offset %d is %4.4x.\n", index, newval);
|
|
#endif
|
|
return 1;
|
|
}
|
|
#endif
|
|
|
|
#ifndef CONFIG_TULIP_FIX_DAVICOM
|
|
static void read_hw_addr(struct eth_device *dev, bd_t *bis)
|
|
{
|
|
u_short tmp, *p = (u_short *)(&dev->enetaddr[0]);
|
|
int i, j = 0;
|
|
|
|
for (i = 0; i < (ETH_ALEN >> 1); i++) {
|
|
tmp = read_srom(dev, DE4X5_APROM, ((SROM_HWADD >> 1) + i));
|
|
*p = le16_to_cpu(tmp);
|
|
j += *p++;
|
|
}
|
|
|
|
if ((j == 0) || (j == 0x2fffd)) {
|
|
memset (dev->enetaddr, 0, ETH_ALEN);
|
|
debug ("Warning: can't read HW address from SROM.\n");
|
|
goto Done;
|
|
}
|
|
|
|
return;
|
|
|
|
Done:
|
|
#ifdef UPDATE_SROM
|
|
update_srom(dev, bis);
|
|
#endif
|
|
return;
|
|
}
|
|
#endif /* CONFIG_TULIP_FIX_DAVICOM */
|
|
|
|
#ifdef UPDATE_SROM
|
|
static void update_srom(struct eth_device *dev, bd_t *bis)
|
|
{
|
|
int i;
|
|
static unsigned short eeprom[0x40] = {
|
|
0x140b, 0x6610, 0x0000, 0x0000, /* 00 */
|
|
0x0000, 0x0000, 0x0000, 0x0000, /* 04 */
|
|
0x00a3, 0x0103, 0x0000, 0x0000, /* 08 */
|
|
0x0000, 0x1f00, 0x0000, 0x0000, /* 0c */
|
|
0x0108, 0x038d, 0x0000, 0x0000, /* 10 */
|
|
0xe078, 0x0001, 0x0040, 0x0018, /* 14 */
|
|
0x0000, 0x0000, 0x0000, 0x0000, /* 18 */
|
|
0x0000, 0x0000, 0x0000, 0x0000, /* 1c */
|
|
0x0000, 0x0000, 0x0000, 0x0000, /* 20 */
|
|
0x0000, 0x0000, 0x0000, 0x0000, /* 24 */
|
|
0x0000, 0x0000, 0x0000, 0x0000, /* 28 */
|
|
0x0000, 0x0000, 0x0000, 0x0000, /* 2c */
|
|
0x0000, 0x0000, 0x0000, 0x0000, /* 30 */
|
|
0x0000, 0x0000, 0x0000, 0x0000, /* 34 */
|
|
0x0000, 0x0000, 0x0000, 0x0000, /* 38 */
|
|
0x0000, 0x0000, 0x0000, 0x4e07, /* 3c */
|
|
};
|
|
uchar enetaddr[6];
|
|
|
|
/* Ethernet Addr... */
|
|
if (!eth_getenv_enetaddr("ethaddr", enetaddr))
|
|
return;
|
|
eeprom[0x0a] = (enetaddr[1] << 8) | enetaddr[0];
|
|
eeprom[0x0b] = (enetaddr[3] << 8) | enetaddr[2];
|
|
eeprom[0x0c] = (enetaddr[5] << 8) | enetaddr[4];
|
|
|
|
for (i=0; i<0x40; i++) {
|
|
write_srom(dev, DE4X5_APROM, i, eeprom[i]);
|
|
}
|
|
}
|
|
#endif /* UPDATE_SROM */
|