mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-16 17:58:23 +00:00
52f52c1494
- add support for Logotronic DL datalogger board - cleanup serial line after kermit binary download - add debugX macro (debug level support) - update mach-types.h to latest arm.linux.org.uk master list.
285 lines
9.1 KiB
C
285 lines
9.1 KiB
C
/*
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* (C) Copyright 2003
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* Robert Schwebel, Pengutronix, r.schwebel@pengutronix.de.
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*
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* Configuration for the Logotronic DL board.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/*
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* include/configs/logodl.h - configuration options, board specific
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* If we are developing, we might want to start U-Boot from ram
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* so we MUST NOT initialize critical regs like mem-timing ...
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*/
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#define CONFIG_INIT_CRITICAL /* undef for developing */
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/*
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* High Level Configuration Options
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* (easy to change)
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*/
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#define CONFIG_PXA250 1 /* This is an PXA250 CPU */
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#define CONFIG_GEALOG 1 /* on a Logotronic GEALOG SG board */
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#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
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/* for timer/console/ethernet */
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/*
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* Hardware drivers
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*/
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/*
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* select serial console configuration
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*/
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#define CONFIG_FFUART 1 /* we use FFUART */
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/* allow to overwrite serial and ethaddr */
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_BAUDRATE 19200
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/*#define CONFIG_MISC_INIT_R 1 / * we have a misc_init_r() function */
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#undef CONFIG_MISC_INIT_R /* FIXME */
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#define CONFIG_COMMANDS (CFG_CMD_FLASH|CFG_CMD_MEMORY|CFG_CMD_ENV|CFG_CMD_RUN|CFG_CMD_ASKENV|CFG_CMD_ECHO)
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/* CONFIG_CMD_DFL|CFG_CMD_I2C|CFG_CMD_EEPROM|CFG_CMD_NET|CFG_CMD_JFFS2|CFG_CMD_DHCP) */
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/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
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#include <cmd_confdefs.h>
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#define CONFIG_BOOTDELAY 3
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/* #define CONFIG_BOOTARGS "root=/dev/nfs ip=bootp console=ttyS0,19200" */
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#define CONFIG_BOOTARGS "console=ttyS0,19200"
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#define CONFIG_ETHADDR FF:FF:FF:FF:FF:FF
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#define CONFIG_NETMASK 255.255.255.0
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#define CONFIG_IPADDR 192.168.1.56
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#define CONFIG_SERVERIP 192.168.1.2
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#define CONFIG_BOOTCOMMAND "bootm 0x40000"
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#define CONFIG_SHOW_BOOT_PROGRESS
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#define CONFIG_CMDLINE_TAG 1
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/*
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* Miscellaneous configurable options
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*/
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/*
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* Size of malloc() pool; this lives below the uppermost 128 KiB which are
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* used for the RAM copy of the uboot code
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*
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*/
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#define CFG_MALLOC_LEN (256*1024)
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#define CFG_LONGHELP /* undef to save memory */
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#define CFG_PROMPT "uboot> " /* Monitor Command Prompt */
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#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
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#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
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#define CFG_MAXARGS 16 /* max number of command args */
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#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
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#define CFG_MEMTEST_START 0x08000000 /* memtest works on */
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#define CFG_MEMTEST_END 0x0800ffff /* 64 KiB */
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#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
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#define CFG_LOAD_ADDR 0x08000000 /* load kernel to this address */
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#define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */
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/* RS: the oscillator is actually 3680130?? */
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#define CFG_CPUSPEED 0x141 /* set core clock to 200/200/100 MHz */
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/* 0101000001 */
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/* ^^^^^ Memory Speed 99.53 MHz */
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/* ^^ Run Mode Speed = 2x Mem Speed */
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/* ^^ Turbo Mode Sp. = 1x Run M. Sp. */
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#define CFG_MONITOR_LEN 0x20000 /* 128 KiB */
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/* valid baudrates */
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#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
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/*
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* SMSC91C111 Network Card
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*/
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/*#define CONFIG_DRIVER_SMC91111 1 */
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/*#define CONFIG_SMC91111_BASE 0x10000000 / * chip select 4 */
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/*#undef CONFIG_SMC_USE_32_BIT / * 16 bit bus access */
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/*#undef CONFIG_SMC_91111_EXT_PHY / * we use internal phy */
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/*#undef CONFIG_SHOW_ACTIVITY */
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/*#define CONFIG_NET_RETRY_COUNT 10 / * # of retries */
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/*
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* Stack sizes
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*
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* The stack sizes are set up in start.S using the settings below
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*/
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#define CONFIG_STACKSIZE (128*1024) /* regular stack */
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#ifdef CONFIG_USE_IRQ
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#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
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#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
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#endif
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/*
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* Physical Memory Map
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*/
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#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of RAM */
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#define PHYS_SDRAM_1 0x08000000 /* SRAM Bank #1 */
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#define PHYS_SDRAM_1_SIZE (4*1024*1024) /* 4 MB */
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#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
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#define PHYS_FLASH_2 0x01000000 /* Flash Bank #2 */
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#define PHYS_FLASH_SIZE (32*1024*1024) /* 32 MB */
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#define CFG_DRAM_BASE PHYS_SDRAM_1 /* RAM starts here */
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#define CFG_DRAM_SIZE PHYS_SDRAM_1_SIZE
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#define CFG_FLASH_BASE PHYS_FLASH_1
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/*
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* GPIO settings
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*
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* GP?? == FOOBAR is 0/1
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*/
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#define _BIT0 0x00000001
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#define _BIT1 0x00000002
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#define _BIT2 0x00000004
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#define _BIT3 0x00000008
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#define _BIT4 0x00000010
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#define _BIT5 0x00000020
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#define _BIT6 0x00000040
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#define _BIT7 0x00000080
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#define _BIT8 0x00000100
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#define _BIT9 0x00000200
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#define _BIT10 0x00000400
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#define _BIT11 0x00000800
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#define _BIT12 0x00001000
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#define _BIT13 0x00002000
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#define _BIT14 0x00004000
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#define _BIT15 0x00008000
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#define _BIT16 0x00010000
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#define _BIT17 0x00020000
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#define _BIT18 0x00040000
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#define _BIT19 0x00080000
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#define _BIT20 0x00100000
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#define _BIT21 0x00200000
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#define _BIT22 0x00400000
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#define _BIT23 0x00800000
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#define _BIT24 0x01000000
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#define _BIT25 0x02000000
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#define _BIT26 0x04000000
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#define _BIT27 0x08000000
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#define _BIT28 0x10000000
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#define _BIT29 0x20000000
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#define _BIT30 0x40000000
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#define _BIT31 0x80000000
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#define CFG_LED_A_BIT (_BIT18)
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#define CFG_LED_A_SR GPSR0
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#define CFG_LED_A_CR GPCR0
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#define CFG_LED_B_BIT (_BIT16)
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#define CFG_LED_B_SR GPSR1
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#define CFG_LED_B_CR GPCR1
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/* LED A: off, LED B: off */
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#define CFG_GPSR0_VAL (_BIT1+_BIT6+_BIT8+_BIT9+_BIT11+_BIT15+_BIT16+_BIT18)
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#define CFG_GPSR1_VAL (_BIT0+_BIT1+_BIT16+_BIT24+_BIT25 +_BIT7+_BIT8+_BIT9+_BIT11+_BIT13)
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#define CFG_GPSR2_VAL (_BIT14+_BIT15+_BIT16)
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#define CFG_GPCR0_VAL 0x00000000
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#define CFG_GPCR1_VAL 0x00000000
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#define CFG_GPCR2_VAL 0x00000000
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#define CFG_GPDR0_VAL (_BIT1+_BIT6+_BIT8+_BIT9+_BIT11+_BIT15+_BIT16+_BIT17+_BIT18)
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#define CFG_GPDR1_VAL (_BIT0+_BIT1+_BIT16+_BIT24+_BIT25 +_BIT7+_BIT8+_BIT9+_BIT11+_BIT13)
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#define CFG_GPDR2_VAL (_BIT14+_BIT15+_BIT16)
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#define CFG_GAFR0_L_VAL (_BIT22+_BIT24+_BIT31)
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#define CFG_GAFR0_U_VAL (_BIT15+_BIT17+_BIT19+\
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_BIT20+_BIT22+_BIT24+_BIT26+_BIT29+_BIT31)
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#define CFG_GAFR1_L_VAL (_BIT3+_BIT4+_BIT6+_BIT8+_BIT10+_BIT12+_BIT15+_BIT17+_BIT19+\
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_BIT20+_BIT23+_BIT24+_BIT27+_BIT28+_BIT31)
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#define CFG_GAFR1_U_VAL (_BIT21+_BIT23+_BIT25+_BIT27+_BIT29+_BIT31)
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#define CFG_GAFR2_L_VAL (_BIT1+_BIT3+_BIT5+_BIT7+_BIT9+_BIT11+_BIT13+_BIT15+_BIT17+\
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_BIT19+_BIT21+_BIT23+_BIT25+_BIT27+_BIT29+_BIT31)
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#define CFG_GAFR2_U_VAL (_BIT1)
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#define CFG_PSSR_VAL (0x20)
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/*
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* Memory settings
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*/
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#define CFG_MSC0_VAL 0x123c2980
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#define CFG_MSC1_VAL 0x123c2661
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#define CFG_MSC2_VAL 0x7ff87ff8
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/* no sdram/pcmcia here */
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#define CFG_MDCNFG_VAL 0x00000000
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#define CFG_MDREFR_VAL 0x00000000
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#define CFG_MDREFR_VAL_100 0x00000000
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#define CFG_MDMRS_VAL 0x00000000
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/* only SRAM */
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#define SXCNFG_SETTINGS 0x00000000
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/*
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* PCMCIA and CF Interfaces
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*/
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#define CFG_MECR_VAL 0x00000000
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#define CFG_MCMEM0_VAL 0x00010504
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#define CFG_MCMEM1_VAL 0x00010504
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#define CFG_MCATT0_VAL 0x00010504
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#define CFG_MCATT1_VAL 0x00010504
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#define CFG_MCIO0_VAL 0x00004715
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#define CFG_MCIO1_VAL 0x00004715
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/*
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* FLASH and environment organization
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*/
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#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
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#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
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/* timeout values are in ticks */
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#define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* Timeout for Flash Erase */
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#define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* Timeout for Flash Write */
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/* FIXME */
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#define CFG_ENV_IS_IN_FLASH 1
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#define CFG_ENV_ADDR (PHYS_FLASH_1 + 0x1C000) /* Addr of Environment Sector */
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#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
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#endif /* __CONFIG_H */
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