mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-05 02:51:00 +00:00
ecfeadabb7
Multiple APs are brought up simultaneously and they may get the same seq num in the uclass_resolve_seq() during device_probe(). To avoid this, set req_seq to the reg number in the device tree in advance. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
526 lines
12 KiB
C
526 lines
12 KiB
C
/*
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* Copyright (C) 2015 Google, Inc
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*
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* SPDX-License-Identifier: GPL-2.0+
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*
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* Based on code from the coreboot file of the same name
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*/
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#include <common.h>
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#include <cpu.h>
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#include <dm.h>
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#include <errno.h>
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#include <malloc.h>
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#include <asm/atomic.h>
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#include <asm/cpu.h>
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#include <asm/interrupt.h>
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#include <asm/lapic.h>
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#include <asm/mp.h>
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#include <asm/msr.h>
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#include <asm/mtrr.h>
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#include <asm/processor.h>
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#include <asm/sipi.h>
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#include <dm/device-internal.h>
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#include <dm/uclass-internal.h>
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#include <linux/linkage.h>
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DECLARE_GLOBAL_DATA_PTR;
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/* Total CPUs include BSP */
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static int num_cpus;
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/* This also needs to match the sipi.S assembly code for saved MSR encoding */
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struct saved_msr {
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uint32_t index;
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uint32_t lo;
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uint32_t hi;
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} __packed;
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struct mp_flight_plan {
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int num_records;
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struct mp_flight_record *records;
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};
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static struct mp_flight_plan mp_info;
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struct cpu_map {
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struct udevice *dev;
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int apic_id;
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int err_code;
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};
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static inline void barrier_wait(atomic_t *b)
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{
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while (atomic_read(b) == 0)
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asm("pause");
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mfence();
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}
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static inline void release_barrier(atomic_t *b)
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{
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mfence();
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atomic_set(b, 1);
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}
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static inline void stop_this_cpu(void)
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{
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/* Called by an AP when it is ready to halt and wait for a new task */
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for (;;)
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cpu_hlt();
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}
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/* Returns 1 if timeout waiting for APs. 0 if target APs found */
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static int wait_for_aps(atomic_t *val, int target, int total_delay,
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int delay_step)
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{
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int timeout = 0;
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int delayed = 0;
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while (atomic_read(val) != target) {
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udelay(delay_step);
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delayed += delay_step;
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if (delayed >= total_delay) {
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timeout = 1;
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break;
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}
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}
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return timeout;
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}
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static void ap_do_flight_plan(struct udevice *cpu)
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{
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int i;
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for (i = 0; i < mp_info.num_records; i++) {
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struct mp_flight_record *rec = &mp_info.records[i];
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atomic_inc(&rec->cpus_entered);
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barrier_wait(&rec->barrier);
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if (rec->ap_call != NULL)
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rec->ap_call(cpu, rec->ap_arg);
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}
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}
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static int find_cpu_by_apid_id(int apic_id, struct udevice **devp)
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{
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struct udevice *dev;
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*devp = NULL;
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for (uclass_find_first_device(UCLASS_CPU, &dev);
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dev;
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uclass_find_next_device(&dev)) {
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struct cpu_platdata *plat = dev_get_parent_platdata(dev);
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if (plat->cpu_id == apic_id) {
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*devp = dev;
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return 0;
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}
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}
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return -ENOENT;
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}
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/*
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* By the time APs call ap_init() caching has been setup, and microcode has
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* been loaded
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*/
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static void ap_init(unsigned int cpu_index)
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{
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struct udevice *dev;
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int apic_id;
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int ret;
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/* Ensure the local apic is enabled */
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enable_lapic();
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apic_id = lapicid();
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ret = find_cpu_by_apid_id(apic_id, &dev);
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if (ret) {
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debug("Unknown CPU apic_id %x\n", apic_id);
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goto done;
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}
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debug("AP: slot %d apic_id %x, dev %s\n", cpu_index, apic_id,
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dev ? dev->name : "(apic_id not found)");
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/* Walk the flight plan */
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ap_do_flight_plan(dev);
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/* Park the AP */
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debug("parking\n");
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done:
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stop_this_cpu();
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}
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static const unsigned int fixed_mtrrs[NUM_FIXED_MTRRS] = {
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MTRR_FIX_64K_00000_MSR, MTRR_FIX_16K_80000_MSR, MTRR_FIX_16K_A0000_MSR,
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MTRR_FIX_4K_C0000_MSR, MTRR_FIX_4K_C8000_MSR, MTRR_FIX_4K_D0000_MSR,
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MTRR_FIX_4K_D8000_MSR, MTRR_FIX_4K_E0000_MSR, MTRR_FIX_4K_E8000_MSR,
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MTRR_FIX_4K_F0000_MSR, MTRR_FIX_4K_F8000_MSR,
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};
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static inline struct saved_msr *save_msr(int index, struct saved_msr *entry)
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{
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msr_t msr;
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msr = msr_read(index);
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entry->index = index;
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entry->lo = msr.lo;
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entry->hi = msr.hi;
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/* Return the next entry */
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entry++;
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return entry;
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}
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static int save_bsp_msrs(char *start, int size)
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{
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int msr_count;
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int num_var_mtrrs;
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struct saved_msr *msr_entry;
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int i;
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msr_t msr;
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/* Determine number of MTRRs need to be saved */
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msr = msr_read(MTRR_CAP_MSR);
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num_var_mtrrs = msr.lo & 0xff;
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/* 2 * num_var_mtrrs for base and mask. +1 for IA32_MTRR_DEF_TYPE */
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msr_count = 2 * num_var_mtrrs + NUM_FIXED_MTRRS + 1;
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if ((msr_count * sizeof(struct saved_msr)) > size) {
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printf("Cannot mirror all %d msrs.\n", msr_count);
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return -ENOSPC;
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}
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msr_entry = (void *)start;
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for (i = 0; i < NUM_FIXED_MTRRS; i++)
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msr_entry = save_msr(fixed_mtrrs[i], msr_entry);
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for (i = 0; i < num_var_mtrrs; i++) {
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msr_entry = save_msr(MTRR_PHYS_BASE_MSR(i), msr_entry);
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msr_entry = save_msr(MTRR_PHYS_MASK_MSR(i), msr_entry);
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}
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msr_entry = save_msr(MTRR_DEF_TYPE_MSR, msr_entry);
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return msr_count;
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}
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static int load_sipi_vector(atomic_t **ap_countp)
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{
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struct sipi_params_16bit *params16;
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struct sipi_params *params;
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static char msr_save[512];
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char *stack;
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ulong addr;
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int code_len;
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int size;
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int ret;
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/* Copy in the code */
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code_len = ap_start16_code_end - ap_start16;
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debug("Copying SIPI code to %x: %d bytes\n", AP_DEFAULT_BASE,
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code_len);
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memcpy((void *)AP_DEFAULT_BASE, ap_start16, code_len);
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addr = AP_DEFAULT_BASE + (ulong)sipi_params_16bit - (ulong)ap_start16;
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params16 = (struct sipi_params_16bit *)addr;
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params16->ap_start = (uint32_t)ap_start;
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params16->gdt = (uint32_t)gd->arch.gdt;
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params16->gdt_limit = X86_GDT_SIZE - 1;
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debug("gdt = %x, gdt_limit = %x\n", params16->gdt, params16->gdt_limit);
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params = (struct sipi_params *)sipi_params;
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debug("SIPI 32-bit params at %p\n", params);
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params->idt_ptr = (uint32_t)x86_get_idt();
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params->stack_size = CONFIG_AP_STACK_SIZE;
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size = params->stack_size * CONFIG_MAX_CPUS;
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stack = memalign(size, 4096);
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if (!stack)
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return -ENOMEM;
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params->stack_top = (u32)(stack + size);
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params->microcode_ptr = 0;
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params->msr_table_ptr = (u32)msr_save;
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ret = save_bsp_msrs(msr_save, sizeof(msr_save));
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if (ret < 0)
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return ret;
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params->msr_count = ret;
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params->c_handler = (uint32_t)&ap_init;
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*ap_countp = ¶ms->ap_count;
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atomic_set(*ap_countp, 0);
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debug("SIPI vector is ready\n");
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return 0;
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}
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static int check_cpu_devices(int expected_cpus)
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{
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int i;
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for (i = 0; i < expected_cpus; i++) {
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struct udevice *dev;
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int ret;
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ret = uclass_find_device(UCLASS_CPU, i, &dev);
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if (ret) {
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debug("Cannot find CPU %d in device tree\n", i);
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return ret;
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}
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}
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return 0;
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}
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/* Returns 1 for timeout. 0 on success */
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static int apic_wait_timeout(int total_delay, int delay_step)
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{
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int total = 0;
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int timeout = 0;
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while (lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY) {
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udelay(delay_step);
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total += delay_step;
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if (total >= total_delay) {
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timeout = 1;
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break;
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}
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}
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return timeout;
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}
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static int start_aps(int ap_count, atomic_t *num_aps)
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{
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int sipi_vector;
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/* Max location is 4KiB below 1MiB */
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const int max_vector_loc = ((1 << 20) - (1 << 12)) >> 12;
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if (ap_count == 0)
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return 0;
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/* The vector is sent as a 4k aligned address in one byte */
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sipi_vector = AP_DEFAULT_BASE >> 12;
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if (sipi_vector > max_vector_loc) {
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printf("SIPI vector too large! 0x%08x\n",
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sipi_vector);
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return -1;
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}
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debug("Attempting to start %d APs\n", ap_count);
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if ((lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY)) {
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debug("Waiting for ICR not to be busy...");
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if (apic_wait_timeout(1000, 50)) {
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debug("timed out. Aborting.\n");
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return -1;
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} else {
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debug("done.\n");
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}
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}
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/* Send INIT IPI to all but self */
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lapic_write(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(0));
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lapic_write(LAPIC_ICR, LAPIC_DEST_ALLBUT | LAPIC_INT_ASSERT |
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LAPIC_DM_INIT);
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debug("Waiting for 10ms after sending INIT.\n");
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mdelay(10);
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/* Send 1st SIPI */
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if ((lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY)) {
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debug("Waiting for ICR not to be busy...");
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if (apic_wait_timeout(1000, 50)) {
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debug("timed out. Aborting.\n");
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return -1;
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} else {
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debug("done.\n");
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}
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}
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lapic_write(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(0));
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lapic_write(LAPIC_ICR, LAPIC_DEST_ALLBUT | LAPIC_INT_ASSERT |
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LAPIC_DM_STARTUP | sipi_vector);
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debug("Waiting for 1st SIPI to complete...");
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if (apic_wait_timeout(10000, 50)) {
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debug("timed out.\n");
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return -1;
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} else {
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debug("done.\n");
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}
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/* Wait for CPUs to check in up to 200 us */
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wait_for_aps(num_aps, ap_count, 200, 15);
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/* Send 2nd SIPI */
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if ((lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY)) {
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debug("Waiting for ICR not to be busy...");
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if (apic_wait_timeout(1000, 50)) {
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debug("timed out. Aborting.\n");
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return -1;
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} else {
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debug("done.\n");
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}
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}
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lapic_write(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(0));
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lapic_write(LAPIC_ICR, LAPIC_DEST_ALLBUT | LAPIC_INT_ASSERT |
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LAPIC_DM_STARTUP | sipi_vector);
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debug("Waiting for 2nd SIPI to complete...");
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if (apic_wait_timeout(10000, 50)) {
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debug("timed out.\n");
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return -1;
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} else {
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debug("done.\n");
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}
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/* Wait for CPUs to check in */
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if (wait_for_aps(num_aps, ap_count, 10000, 50)) {
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debug("Not all APs checked in: %d/%d.\n",
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atomic_read(num_aps), ap_count);
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return -1;
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}
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return 0;
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}
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static int bsp_do_flight_plan(struct udevice *cpu, struct mp_params *mp_params)
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{
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int i;
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int ret = 0;
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const int timeout_us = 100000;
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const int step_us = 100;
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int num_aps = num_cpus - 1;
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for (i = 0; i < mp_params->num_records; i++) {
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struct mp_flight_record *rec = &mp_params->flight_plan[i];
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/* Wait for APs if the record is not released */
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if (atomic_read(&rec->barrier) == 0) {
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/* Wait for the APs to check in */
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if (wait_for_aps(&rec->cpus_entered, num_aps,
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timeout_us, step_us)) {
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debug("MP record %d timeout.\n", i);
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ret = -1;
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}
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}
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if (rec->bsp_call != NULL)
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rec->bsp_call(cpu, rec->bsp_arg);
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release_barrier(&rec->barrier);
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}
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return ret;
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}
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static int init_bsp(struct udevice **devp)
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{
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char processor_name[CPU_MAX_NAME_LEN];
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int apic_id;
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int ret;
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cpu_get_name(processor_name);
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debug("CPU: %s.\n", processor_name);
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lapic_setup();
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apic_id = lapicid();
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ret = find_cpu_by_apid_id(apic_id, devp);
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if (ret) {
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printf("Cannot find boot CPU, APIC ID %d\n", apic_id);
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return ret;
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}
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return 0;
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}
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int mp_init(struct mp_params *p)
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{
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int num_aps;
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atomic_t *ap_count;
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struct udevice *cpu;
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int ret;
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/* This will cause the CPUs devices to be bound */
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struct uclass *uc;
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ret = uclass_get(UCLASS_CPU, &uc);
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if (ret)
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return ret;
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ret = init_bsp(&cpu);
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if (ret) {
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debug("Cannot init boot CPU: err=%d\n", ret);
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return ret;
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}
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if (p == NULL || p->flight_plan == NULL || p->num_records < 1) {
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printf("Invalid MP parameters\n");
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return -1;
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}
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num_cpus = cpu_get_count(cpu);
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if (num_cpus < 0) {
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debug("Cannot get number of CPUs: err=%d\n", num_cpus);
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return num_cpus;
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}
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if (num_cpus < 2)
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debug("Warning: Only 1 CPU is detected\n");
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ret = check_cpu_devices(num_cpus);
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if (ret)
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debug("Warning: Device tree does not describe all CPUs. Extra ones will not be started correctly\n");
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/* Copy needed parameters so that APs have a reference to the plan */
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mp_info.num_records = p->num_records;
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mp_info.records = p->flight_plan;
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/* Load the SIPI vector */
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ret = load_sipi_vector(&ap_count);
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if (ap_count == NULL)
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return -1;
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/*
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* Make sure SIPI data hits RAM so the APs that come up will see
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* the startup code even if the caches are disabled
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*/
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wbinvd();
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/* Start the APs providing number of APs and the cpus_entered field */
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num_aps = num_cpus - 1;
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ret = start_aps(num_aps, ap_count);
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if (ret) {
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mdelay(1000);
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debug("%d/%d eventually checked in?\n", atomic_read(ap_count),
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num_aps);
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return ret;
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}
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/* Walk the flight plan for the BSP */
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ret = bsp_do_flight_plan(cpu, p);
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if (ret) {
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debug("CPU init failed: err=%d\n", ret);
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return ret;
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}
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return 0;
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}
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int mp_init_cpu(struct udevice *cpu, void *unused)
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{
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/*
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* Multiple APs are brought up simultaneously and they may get the same
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* seq num in the uclass_resolve_seq() during device_probe(). To avoid
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* this, set req_seq to the reg number in the device tree in advance.
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*/
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cpu->req_seq = fdtdec_get_int(gd->fdt_blob, cpu->of_offset, "reg", -1);
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return device_probe(cpu);
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}
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