mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-05 02:51:00 +00:00
b58385df3a
Add missing L3 cache flush functionality which absence prevents Linux kernel from normal boot in case the L3 cache is enabled by ATF. The L3 cache is named the "last level" cache in order to keep the terminology similar to the ATF code. This cache should not be disabled by u-boot since the Linux kernel cannot activate it, so it is activates at ATF stage. However the cache flush is required for preventing data corruption after disabling the MMU and the data cache before passing control to the loaded Linux image. Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Cc: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Neta Zur Hershkovits <neta@marvell.com> Cc: Omri Itach <omrii@marvell.com> Cc: Igal Liberman <igall@marvell.com> Cc: Haim Boot <hayim@marvell.com> Cc: Hanna Hawa <hannah@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
21 lines
475 B
C
21 lines
475 B
C
/*
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* Copyright (C) 2016 Marvell International Ltd.
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*
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* SPDX-License-Identifier: GPL-2.0
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* https://spdx.org/licenses
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*/
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#ifndef _CACHE_LLC_H_
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#define _CACHE_LLC_H_
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/* Armada-7K/8K last level cache */
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#define MVEBU_A8K_REGS_BASE_MSB 0xf000
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#define LLC_BASE_ADDR 0x8000
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#define LLC_CACHE_SYNC 0x700
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#define LLC_CACHE_SYNC_COMPLETE 0x730
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#define LLC_FLUSH_BY_WAY 0x7fc
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#define LLC_WAY_MASK 0xffffffff
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#define LLC_CACHE_SYNC_MASK 0x1
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#endif /* _CACHE_LLC_H_ */
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