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https://github.com/AsahiLinux/u-boot
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1a4596601f
Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com>
138 lines
2.8 KiB
C
138 lines
2.8 KiB
C
/*
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* (C) Copyright 2011, Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
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* (C) Copyright 2011, Julius Baxter <julius@opencores.org>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/system.h>
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void flush_dcache_range(unsigned long addr, unsigned long stop)
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{
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ulong block_size = (mfspr(SPR_DCCFGR) & SPR_DCCFGR_CBS) ? 32 : 16;
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while (addr < stop) {
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mtspr(SPR_DCBFR, addr);
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addr += block_size;
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}
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}
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void invalidate_dcache_range(unsigned long addr, unsigned long stop)
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{
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ulong block_size = (mfspr(SPR_DCCFGR) & SPR_DCCFGR_CBS) ? 32 : 16;
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while (addr < stop) {
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mtspr(SPR_DCBIR, addr);
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addr += block_size;
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}
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}
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static void invalidate_icache_range(unsigned long addr, unsigned long stop)
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{
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ulong block_size = (mfspr(SPR_ICCFGR) & SPR_ICCFGR_CBS) ? 32 : 16;
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while (addr < stop) {
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mtspr(SPR_ICBIR, addr);
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addr += block_size;
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}
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}
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void flush_cache(unsigned long addr, unsigned long size)
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{
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flush_dcache_range(addr, addr + size);
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invalidate_icache_range(addr, addr + size);
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}
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int icache_status(void)
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{
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return mfspr(SPR_SR) & SPR_SR_ICE;
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}
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int checkicache(void)
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{
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unsigned long iccfgr;
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unsigned long cache_set_size;
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unsigned long cache_ways;
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unsigned long cache_block_size;
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iccfgr = mfspr(SPR_ICCFGR);
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cache_ways = 1 << (iccfgr & SPR_ICCFGR_NCW);
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cache_set_size = 1 << ((iccfgr & SPR_ICCFGR_NCS) >> 3);
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cache_block_size = (iccfgr & SPR_ICCFGR_CBS) ? 32 : 16;
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return cache_set_size * cache_ways * cache_block_size;
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}
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int dcache_status(void)
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{
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return mfspr(SPR_SR) & SPR_SR_DCE;
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}
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int checkdcache(void)
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{
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unsigned long dccfgr;
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unsigned long cache_set_size;
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unsigned long cache_ways;
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unsigned long cache_block_size;
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dccfgr = mfspr(SPR_DCCFGR);
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cache_ways = 1 << (dccfgr & SPR_DCCFGR_NCW);
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cache_set_size = 1 << ((dccfgr & SPR_DCCFGR_NCS) >> 3);
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cache_block_size = (dccfgr & SPR_DCCFGR_CBS) ? 32 : 16;
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return cache_set_size * cache_ways * cache_block_size;
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}
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void dcache_enable(void)
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{
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mtspr(SPR_SR, mfspr(SPR_SR) | SPR_SR_DCE);
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asm volatile("l.nop");
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asm volatile("l.nop");
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asm volatile("l.nop");
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asm volatile("l.nop");
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asm volatile("l.nop");
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asm volatile("l.nop");
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asm volatile("l.nop");
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asm volatile("l.nop");
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}
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void dcache_disable(void)
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{
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mtspr(SPR_SR, mfspr(SPR_SR) & ~SPR_SR_DCE);
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}
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void icache_enable(void)
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{
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mtspr(SPR_SR, mfspr(SPR_SR) | SPR_SR_ICE);
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asm volatile("l.nop");
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asm volatile("l.nop");
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asm volatile("l.nop");
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asm volatile("l.nop");
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asm volatile("l.nop");
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asm volatile("l.nop");
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asm volatile("l.nop");
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asm volatile("l.nop");
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}
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void icache_disable(void)
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{
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mtspr(SPR_SR, mfspr(SPR_SR) & ~SPR_SR_ICE);
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}
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int cache_init(void)
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{
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if (mfspr(SPR_UPR) & SPR_UPR_ICP) {
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icache_disable();
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invalidate_icache_range(0, checkicache());
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icache_enable();
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}
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if (mfspr(SPR_UPR) & SPR_UPR_DCP) {
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dcache_disable();
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invalidate_dcache_range(0, checkdcache());
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dcache_enable();
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}
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return 0;
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}
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