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https://github.com/AsahiLinux/u-boot
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58c3e62040
LX2160ARDB is an evaluation board that supports LX2160A family SoCs. This patch add base support for this board. Signed-off-by: Wasim Khan <wasim.khan@nxp.com> Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Peng Ma <peng.ma@nxp.com> Signed-off-by: Chuanhua Han <chuanhua.han@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> [PK: Sqaush patches from Yinbo Zhu, Peng Ma, Chuanhua Han and re-arrange defconfig] Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
279 lines
5.3 KiB
C
279 lines
5.3 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2018 NXP
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*/
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#include <common.h>
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#include <dm.h>
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#include <dm/platform_data/serial_pl01x.h>
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#include <i2c.h>
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#include <malloc.h>
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#include <errno.h>
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#include <netdev.h>
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#include <fsl_ddr.h>
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#include <fsl_sec.h>
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#include <asm/io.h>
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#include <fdt_support.h>
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#include <linux/libfdt.h>
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#include <fsl-mc/fsl_mc.h>
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#include <environment.h>
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#include <efi_loader.h>
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#include <asm/arch/mmu.h>
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#include <hwconfig.h>
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#include <asm/arch/fsl_serdes.h>
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#include <asm/arch/soc.h>
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#include "../common/qixis.h"
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#include "../common/vid.h"
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#include <fsl_immap.h>
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DECLARE_GLOBAL_DATA_PTR;
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static struct pl01x_serial_platdata serial0 = {
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#if CONFIG_CONS_INDEX == 0
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.base = CONFIG_SYS_SERIAL0,
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#elif CONFIG_CONS_INDEX == 1
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.base = CONFIG_SYS_SERIAL1,
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#else
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#error "Unsupported console index value."
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#endif
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.type = TYPE_PL011,
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};
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U_BOOT_DEVICE(nxp_serial0) = {
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.name = "serial_pl01x",
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.platdata = &serial0,
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};
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static struct pl01x_serial_platdata serial1 = {
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.base = CONFIG_SYS_SERIAL1,
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.type = TYPE_PL011,
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};
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U_BOOT_DEVICE(nxp_serial1) = {
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.name = "serial_pl01x",
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.platdata = &serial1,
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};
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int select_i2c_ch_pca9547(u8 ch)
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{
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int ret;
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ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
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if (ret) {
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puts("PCA: failed to select proper channel\n");
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return ret;
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}
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return 0;
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}
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static void uart_get_clock(void)
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{
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serial0.clock = get_serial_clock();
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serial1.clock = get_serial_clock();
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}
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int board_early_init_f(void)
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{
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#ifdef CONFIG_SYS_I2C_EARLY_INIT
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i2c_early_init_f();
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#endif
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/* get required clock for UART IP */
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uart_get_clock();
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fsl_lsch3_early_init_f();
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return 0;
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}
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int esdhc_status_fixup(void *blob, const char *compat)
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{
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/* Enable both esdhc DT nodes for LX2160ARDB */
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do_fixup_by_compat(blob, compat, "status", "okay",
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sizeof("okay"), 1);
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return 0;
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}
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#if defined(CONFIG_VID)
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int i2c_multiplexer_select_vid_channel(u8 channel)
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{
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return select_i2c_ch_pca9547(channel);
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}
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#endif
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int checkboard(void)
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{
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enum boot_src src = get_boot_src();
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char buf[64];
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u8 sw;
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cpu_name(buf);
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printf("Board: %s-RDB, ", buf);
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sw = QIXIS_READ(arch);
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printf("Board version: %c, boot from ", (sw & 0xf) - 1 + 'A');
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if (src == BOOT_SOURCE_SD_MMC) {
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puts("SD\n");
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} else {
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sw = QIXIS_READ(brdcfg[0]);
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sw = (sw >> QIXIS_XMAP_SHIFT) & QIXIS_XMAP_MASK;
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switch (sw) {
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case 0:
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case 4:
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puts("FlexSPI DEV#0\n");
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break;
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case 1:
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puts("FlexSPI DEV#1\n");
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break;
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case 2:
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case 3:
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puts("FlexSPI EMU\n");
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break;
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default:
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printf("invalid setting, xmap: %d\n", sw);
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break;
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}
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}
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printf("FPGA: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata));
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puts("SERDES1 Reference: Clock1 = 161.13MHz Clock2 = 161.13MHz\n");
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puts("SERDES2 Reference: Clock1 = 100MHz Clock2 = 100MHz\n");
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puts("SERDES3 Reference: Clock1 = 100MHz Clock2 = 100Hz\n");
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return 0;
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}
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unsigned long get_board_sys_clk(void)
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{
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return 100000000;
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}
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unsigned long get_board_ddr_clk(void)
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{
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return 100000000;
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}
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int board_init(void)
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{
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#ifdef CONFIG_ENV_IS_NOWHERE
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gd->env_addr = (ulong)&default_environment[0];
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#endif
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select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
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#ifdef CONFIG_FSL_CAAM
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sec_init();
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#endif
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return 0;
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}
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void detail_board_ddr_info(void)
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{
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int i;
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u64 ddr_size = 0;
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puts("\nDDR ");
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for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
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ddr_size += gd->bd->bi_dram[i].size;
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print_size(ddr_size, "");
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print_ddr_info(0);
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}
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#if defined(CONFIG_ARCH_MISC_INIT)
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int arch_misc_init(void)
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{
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return 0;
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}
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#endif
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#ifdef CONFIG_FSL_MC_ENET
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extern int fdt_fixup_board_phy(void *fdt);
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void fdt_fixup_board_enet(void *fdt)
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{
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int offset;
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offset = fdt_path_offset(fdt, "/soc/fsl-mc");
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if (offset < 0)
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offset = fdt_path_offset(fdt, "/fsl-mc");
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if (offset < 0) {
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printf("%s: fsl-mc node not found in device tree (error %d)\n",
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__func__, offset);
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return;
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}
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if ((get_mc_boot_status() == 0) && (get_dpl_apply_status() == 0)) {
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fdt_status_okay(fdt, offset);
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fdt_fixup_board_phy(fdt);
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} else {
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fdt_status_fail(fdt, offset);
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}
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}
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void board_quiesce_devices(void)
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{
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fsl_mc_ldpaa_exit(gd->bd);
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}
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#endif
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#ifdef CONFIG_OF_BOARD_SETUP
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int ft_board_setup(void *blob, bd_t *bd)
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{
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int i;
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u64 base[CONFIG_NR_DRAM_BANKS];
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u64 size[CONFIG_NR_DRAM_BANKS];
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ft_cpu_setup(blob, bd);
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/* fixup DT for the three GPP DDR banks */
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for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
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base[i] = gd->bd->bi_dram[i].start;
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size[i] = gd->bd->bi_dram[i].size;
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}
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#ifdef CONFIG_RESV_RAM
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/* reduce size if reserved memory is within this bank */
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if (gd->arch.resv_ram >= base[0] &&
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gd->arch.resv_ram < base[0] + size[0])
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size[0] = gd->arch.resv_ram - base[0];
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else if (gd->arch.resv_ram >= base[1] &&
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gd->arch.resv_ram < base[1] + size[1])
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size[1] = gd->arch.resv_ram - base[1];
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else if (gd->arch.resv_ram >= base[2] &&
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gd->arch.resv_ram < base[2] + size[2])
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size[2] = gd->arch.resv_ram - base[2];
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#endif
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fdt_fixup_memory_banks(blob, base, size, CONFIG_NR_DRAM_BANKS);
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#ifdef CONFIG_USB
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fsl_fdt_fixup_dr_usb(blob, bd);
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#endif
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#ifdef CONFIG_FSL_MC_ENET
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fdt_fsl_mc_fixup_iommu_map_entry(blob);
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fdt_fixup_board_enet(blob);
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#endif
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return 0;
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}
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#endif
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void qixis_dump_switch(void)
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{
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int i, nr_of_cfgsw;
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QIXIS_WRITE(cms[0], 0x00);
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nr_of_cfgsw = QIXIS_READ(cms[1]);
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puts("DIP switch settings dump:\n");
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for (i = 1; i <= nr_of_cfgsw; i++) {
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QIXIS_WRITE(cms[0], i);
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printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));
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}
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}
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