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https://github.com/AsahiLinux/u-boot
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814e1a4b8c
Create a non-cacheable mapping for the 0x600000000 physical memory region, where MMIO registers for the PCIe XHCI controller are instantiated by the PCIe bridge. Due to 32bit limit in the CPU virtual address space in ARM 32bit mode, this region is mapped at 0xff800000 CPU virtual address. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
19 lines
361 B
C
19 lines
361 B
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* (C) Copyright 2019 Matthias Brugger
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*/
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#ifndef _BCM283x_BASE_H_
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#define _BCM283x_BASE_H_
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extern unsigned long rpi_bcm283x_base;
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#ifdef CONFIG_ARMV7_LPAE
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#ifdef CONFIG_TARGET_RPI_4_32B
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#include <addr_map.h>
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#define phys_to_virt addrmap_phys_to_virt
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#define virt_to_phys addrmap_virt_to_phys
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#endif
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#endif
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#endif
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