mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-14 17:07:38 +00:00
61290fb52c
QCA9563 is CPU used on AP152 board :
Clock speed : 750 MHz ,
Arch : Mips 74Kc,
Eth : SGMII interface,
MIMO config : 3 * 3 450M,
2 * USB 2.0,
Signed-off-by: Rosy Song <rosysong@rosinson.com>
Changes for v2:
- coding style cleanup
- remove ununsed flash chip in defconfig
- enable automatic icache / dcache size in defconfig
Changes for v3:
- add detailed information for qca956x in commit message
Changes for v4:
- remove pre-configured network settings in ap152.h
Changes for v5:
- coding style cleanup
308 lines
12 KiB
C
308 lines
12 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2019 Rosy Song <rosysong@rosinson.com>
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*
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* Based on QSDK
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/addrspace.h>
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#include <asm/types.h>
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#include <mach/ar71xx_regs.h>
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#include <mach/ath79.h>
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#define DDR_FSM_WAIT_CTRL_VAL 0xa12
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#define DDR_CTL_CONFIG_SRAM_TSEL_LSB 30
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#define DDR_CTL_CONFIG_SRAM_TSEL_MASK 0xc0000000
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#define DDR_CTL_CONFIG_SRAM_TSEL_SET(x) \
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(((x) << DDR_CTL_CONFIG_SRAM_TSEL_LSB) & DDR_CTL_CONFIG_SRAM_TSEL_MASK)
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#define DDR_CTL_CONFIG_GE0_SRAM_SYNC_LSB 20
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#define DDR_CTL_CONFIG_GE0_SRAM_SYNC_MASK 0x00100000
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#define DDR_CTL_CONFIG_GE0_SRAM_SYNC_SET(x) \
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(((x) << DDR_CTL_CONFIG_GE0_SRAM_SYNC_LSB) & DDR_CTL_CONFIG_GE0_SRAM_SYNC_MASK)
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#define DDR_CTL_CONFIG_GE1_SRAM_SYNC_LSB 19
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#define DDR_CTL_CONFIG_GE1_SRAM_SYNC_MASK 0x00080000
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#define DDR_CTL_CONFIG_GE1_SRAM_SYNC_SET(x) \
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(((x) << DDR_CTL_CONFIG_GE1_SRAM_SYNC_LSB) & DDR_CTL_CONFIG_GE1_SRAM_SYNC_MASK)
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#define DDR_CTL_CONFIG_USB_SRAM_SYNC_LSB 18
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#define DDR_CTL_CONFIG_USB_SRAM_SYNC_MASK 0x00040000
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#define DDR_CTL_CONFIG_USB_SRAM_SYNC_SET(x) \
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(((x) << DDR_CTL_CONFIG_USB_SRAM_SYNC_LSB) & DDR_CTL_CONFIG_USB_SRAM_SYNC_MASK)
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#define DDR_CTL_CONFIG_PCIE_SRAM_SYNC_LSB 17
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#define DDR_CTL_CONFIG_PCIE_SRAM_SYNC_MASK 0x00020000
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#define DDR_CTL_CONFIG_PCIE_SRAM_SYNC_SET(x) \
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(((x) << DDR_CTL_CONFIG_PCIE_SRAM_SYNC_LSB) & DDR_CTL_CONFIG_PCIE_SRAM_SYNC_MASK)
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#define DDR_CTL_CONFIG_WMAC_SRAM_SYNC_LSB 16
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#define DDR_CTL_CONFIG_WMAC_SRAM_SYNC_MASK 0x00010000
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#define DDR_CTL_CONFIG_WMAC_SRAM_SYNC_SET(x) \
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(((x) << DDR_CTL_CONFIG_WMAC_SRAM_SYNC_LSB) & DDR_CTL_CONFIG_WMAC_SRAM_SYNC_MASK)
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#define DDR_CTL_CONFIG_MISC_SRC1_SRAM_SYNC_LSB 15
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#define DDR_CTL_CONFIG_MISC_SRC1_SRAM_SYNC_MASK 0x00008000
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#define DDR_CTL_CONFIG_MISC_SRC1_SRAM_SYNC_SET(x) \
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(((x) << DDR_CTL_CONFIG_MISC_SRC1_SRAM_SYNC_LSB) & DDR_CTL_CONFIG_MISC_SRC1_SRAM_SYNC_MASK)
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#define DDR_CTL_CONFIG_MISC_SRC2_SRAM_SYNC_LSB 14
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#define DDR_CTL_CONFIG_MISC_SRC2_SRAM_SYNC_MASK 0x00004000
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#define DDR_CTL_CONFIG_MISC_SRC2_SRAM_SYNC_SET(x) \
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(((x) << DDR_CTL_CONFIG_MISC_SRC2_SRAM_SYNC_LSB) & DDR_CTL_CONFIG_MISC_SRC2_SRAM_SYNC_MASK)
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#define DDR_CTL_CONFIG_PAD_DDR2_SEL_LSB 6
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#define DDR_CTL_CONFIG_PAD_DDR2_SEL_MASK 0x00000040
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#define DDR_CTL_CONFIG_PAD_DDR2_SEL_SET(x) \
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(((x) << DDR_CTL_CONFIG_PAD_DDR2_SEL_LSB) & DDR_CTL_CONFIG_PAD_DDR2_SEL_MASK)
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#define DDR_CTL_CONFIG_CPU_DDR_SYNC_LSB 2
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#define DDR_CTL_CONFIG_CPU_DDR_SYNC_MASK 0x00000004
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#define DDR_CTL_CONFIG_CPU_DDR_SYNC_SET(x) \
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(((x) << DDR_CTL_CONFIG_CPU_DDR_SYNC_LSB) & DDR_CTL_CONFIG_CPU_DDR_SYNC_MASK)
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#define DDR_CTL_CONFIG_HALF_WIDTH_LSB 1
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#define DDR_CTL_CONFIG_HALF_WIDTH_MASK 0x00000002
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#define DDR_CTL_CONFIG_HALF_WIDTH_SET(x) \
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(((x) << DDR_CTL_CONFIG_HALF_WIDTH_LSB) & DDR_CTL_CONFIG_HALF_WIDTH_MASK)
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#define DDR_CONFIG_CAS_LATENCY_MSB_LSB 31
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#define DDR_CONFIG_CAS_LATENCY_MSB_MASK 0x80000000
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#define DDR_CONFIG_CAS_LATENCY_MSB_SET(x) \
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(((x) << DDR_CONFIG_CAS_LATENCY_MSB_LSB) & DDR_CONFIG_CAS_LATENCY_MSB_MASK)
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#define DDR_CONFIG_OPEN_PAGE_LSB 30
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#define DDR_CONFIG_OPEN_PAGE_MASK 0x40000000
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#define DDR_CONFIG_OPEN_PAGE_SET(x) \
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(((x) << DDR_CONFIG_OPEN_PAGE_LSB) & DDR_CONFIG_OPEN_PAGE_MASK)
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#define DDR_CONFIG_CAS_LATENCY_LSB 27
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#define DDR_CONFIG_CAS_LATENCY_MASK 0x38000000
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#define DDR_CONFIG_CAS_LATENCY_SET(x) \
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(((x) << DDR_CONFIG_CAS_LATENCY_LSB) & DDR_CONFIG_CAS_LATENCY_MASK)
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#define DDR_CONFIG_TMRD_LSB 23
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#define DDR_CONFIG_TMRD_MASK 0x07800000
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#define DDR_CONFIG_TMRD_SET(x) \
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(((x) << DDR_CONFIG_TMRD_LSB) & DDR_CONFIG_TMRD_MASK)
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#define DDR_CONFIG_TRFC_LSB 17
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#define DDR_CONFIG_TRFC_MASK 0x007e0000
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#define DDR_CONFIG_TRFC_SET(x) \
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(((x) << DDR_CONFIG_TRFC_LSB) & DDR_CONFIG_TRFC_MASK)
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#define DDR_CONFIG_TRRD_LSB 13
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#define DDR_CONFIG_TRRD_MASK 0x0001e000
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#define DDR_CONFIG_TRRD_SET(x) \
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(((x) << DDR_CONFIG_TRRD_LSB) & DDR_CONFIG_TRRD_MASK)
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#define DDR_CONFIG_TRP_LSB 9
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#define DDR_CONFIG_TRP_MASK 0x00001e00
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#define DDR_CONFIG_TRP_SET(x) \
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(((x) << DDR_CONFIG_TRP_LSB) & DDR_CONFIG_TRP_MASK)
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#define DDR_CONFIG_TRCD_LSB 5
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#define DDR_CONFIG_TRCD_MASK 0x000001e0
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#define DDR_CONFIG_TRCD_SET(x) \
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(((x) << DDR_CONFIG_TRCD_LSB) & DDR_CONFIG_TRCD_MASK)
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#define DDR_CONFIG_TRAS_LSB 0
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#define DDR_CONFIG_TRAS_MASK 0x0000001f
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#define DDR_CONFIG_TRAS_SET(x) \
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(((x) << DDR_CONFIG_TRAS_LSB) & DDR_CONFIG_TRAS_MASK)
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#define DDR_CONFIG2_HALF_WIDTH_LOW_LSB 31
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#define DDR_CONFIG2_HALF_WIDTH_LOW_MASK 0x80000000
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#define DDR_CONFIG2_HALF_WIDTH_LOW_SET(x) \
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(((x) << DDR_CONFIG2_HALF_WIDTH_LOW_LSB) & DDR_CONFIG2_HALF_WIDTH_LOW_MASK)
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#define DDR_CONFIG2_SWAP_A26_A27_LSB 30
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#define DDR_CONFIG2_SWAP_A26_A27_MASK 0x40000000
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#define DDR_CONFIG2_SWAP_A26_A27_SET(x) \
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(((x) << DDR_CONFIG2_SWAP_A26_A27_LSB) & DDR_CONFIG2_SWAP_A26_A27_MASK)
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#define DDR_CONFIG2_GATE_OPEN_LATENCY_LSB 26
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#define DDR_CONFIG2_GATE_OPEN_LATENCY_MASK 0x3c000000
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#define DDR_CONFIG2_GATE_OPEN_LATENCY_SET(x) \
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(((x) << DDR_CONFIG2_GATE_OPEN_LATENCY_LSB) & DDR_CONFIG2_GATE_OPEN_LATENCY_MASK)
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#define DDR_CONFIG2_TWTR_LSB 21
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#define DDR_CONFIG2_TWTR_MASK 0x03e00000
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#define DDR_CONFIG2_TWTR_SET(x) \
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(((x) << DDR_CONFIG2_TWTR_LSB) & DDR_CONFIG2_TWTR_MASK)
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#define DDR_CONFIG2_TRTP_LSB 17
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#define DDR_CONFIG2_TRTP_MASK 0x001e0000
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#define DDR_CONFIG2_TRTP_SET(x) \
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(((x) << DDR_CONFIG2_TRTP_LSB) & DDR_CONFIG2_TRTP_MASK)
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#define DDR_CONFIG2_TRTW_LSB 12
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#define DDR_CONFIG2_TRTW_MASK 0x0001f000
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#define DDR_CONFIG2_TRTW_SET(x) \
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(((x) << DDR_CONFIG2_TRTW_LSB) & DDR_CONFIG2_TRTW_MASK)
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#define DDR_CONFIG2_TWR_LSB 8
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#define DDR_CONFIG2_TWR_MASK 0x00000f00
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#define DDR_CONFIG2_TWR_SET(x) \
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(((x) << DDR_CONFIG2_TWR_LSB) & DDR_CONFIG2_TWR_MASK)
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#define DDR_CONFIG2_CKE_LSB 7
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#define DDR_CONFIG2_CKE_MASK 0x00000080
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#define DDR_CONFIG2_CKE_SET(x) \
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(((x) << DDR_CONFIG2_CKE_LSB) & DDR_CONFIG2_CKE_MASK)
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#define DDR_CONFIG2_CNTL_OE_EN_LSB 5
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#define DDR_CONFIG2_CNTL_OE_EN_MASK 0x00000020
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#define DDR_CONFIG2_CNTL_OE_EN_SET(x) \
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(((x) << DDR_CONFIG2_CNTL_OE_EN_LSB) & DDR_CONFIG2_CNTL_OE_EN_MASK)
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#define DDR_CONFIG2_BURST_LENGTH_LSB 0
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#define DDR_CONFIG2_BURST_LENGTH_MASK 0x0000000f
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#define DDR_CONFIG2_BURST_LENGTH_SET(x) \
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(((x) << DDR_CONFIG2_BURST_LENGTH_LSB) & DDR_CONFIG2_BURST_LENGTH_MASK)
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#define RST_BOOTSTRAP_ADDRESS 0x180600b0
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#define PMU2_SWREGMSB_LSB 22
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#define PMU2_SWREGMSB_MASK 0xffc00000
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#define PMU2_SWREGMSB_SET(x) \
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(((x) << PMU2_SWREGMSB_LSB) & PMU2_SWREGMSB_MASK)
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#define PMU2_PGM_LSB 21
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#define PMU2_PGM_MASK 0x00200000
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#define PMU2_PGM_SET(x) \
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(((x) << PMU2_PGM_LSB) & PMU2_PGM_MASK)
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#define CPU_DDR_SYNC_MODE DDR_CTL_CONFIG_CPU_DDR_SYNC_SET(0)
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/*
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* DDR2 DDR1
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* 0x40c3 25MHz 0x4186 25Mhz
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* 0x4138 40MHz 0x4270 40Mhz
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*/
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#define CFG_DDR2_REFRESH_VAL 0x40c3
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#define CFG_DDR2_CONFIG_VAL DDR_CONFIG_CAS_LATENCY_MSB_SET(0x1) | \
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DDR_CONFIG_OPEN_PAGE_SET(0x1) | DDR_CONFIG_CAS_LATENCY_SET(0x4) | \
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DDR_CONFIG_TMRD_SET(0x6) | DDR_CONFIG_TRFC_SET(0x16) | \
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DDR_CONFIG_TRRD_SET(0x7) | DDR_CONFIG_TRP_SET(0xb) | \
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DDR_CONFIG_TRCD_SET(0xb) | DDR_CONFIG_TRAS_SET(0)
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#define CFG_DDR2_CONFIG2_VAL DDR_CONFIG2_HALF_WIDTH_LOW_SET(0x1) | \
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DDR_CONFIG2_SWAP_A26_A27_SET(0x0) | DDR_CONFIG2_GATE_OPEN_LATENCY_SET(0xa) | \
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DDR_CONFIG2_TWTR_SET(0x16) | DDR_CONFIG2_TRTP_SET(0xa) | \
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DDR_CONFIG2_TRTW_SET(0xe) | DDR_CONFIG2_TWR_SET(0x2) | \
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DDR_CONFIG2_CKE_SET(0x1) | DDR_CONFIG2_CNTL_OE_EN_SET(0x1) | \
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DDR_CONFIG2_BURST_LENGTH_SET(0x8)
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#define CFG_DDR2_CONFIG3_VAL 0x0000000e
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#define CFG_DDR2_EXT_MODE_VAL1 0x782
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#define CFG_DDR2_EXT_MODE_VAL2 0x402
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#define CFG_DDR2_MODE_VAL_INIT 0xb53
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#define CFG_DDR2_MODE_VAL 0xa53
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#define CFG_DDR2_TAP_VAL 0x10
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#define CFG_DDR2_EN_TWL_VAL 0x00001e91
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#define CFG_DDR2_RD_DATA_THIS_CYCLE_VAL_16 0xffff
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#define CFG_DDR_CTL_CONFIG DDR_CTL_CONFIG_SRAM_TSEL_SET(0x1) | \
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DDR_CTL_CONFIG_GE0_SRAM_SYNC_SET(0x1) | \
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DDR_CTL_CONFIG_GE1_SRAM_SYNC_SET(0x1) | \
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DDR_CTL_CONFIG_USB_SRAM_SYNC_SET(0x1) | \
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DDR_CTL_CONFIG_PCIE_SRAM_SYNC_SET(0x1) | \
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DDR_CTL_CONFIG_WMAC_SRAM_SYNC_SET(0x1) | \
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DDR_CTL_CONFIG_MISC_SRC1_SRAM_SYNC_SET(0x1) | \
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DDR_CTL_CONFIG_MISC_SRC2_SRAM_SYNC_SET(0x1)
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DECLARE_GLOBAL_DATA_PTR;
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void qca956x_ddr_init(void)
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{
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u32 ddr_config, ddr_config2, ddr_config3, mod_val, \
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mod_val_init, cycle_val, tap_val, ctl_config;
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void __iomem *ddr_regs = map_physmem(AR71XX_DDR_CTRL_BASE, AR71XX_DDR_CTRL_SIZE,
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MAP_NOCACHE);
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void __iomem *srif_regs = map_physmem(QCA956X_SRIF_BASE, QCA956X_SRIF_SIZE,
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MAP_NOCACHE);
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ddr_config = CFG_DDR2_CONFIG_VAL;
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ddr_config2 = CFG_DDR2_CONFIG2_VAL;
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ddr_config3 = CFG_DDR2_CONFIG3_VAL;
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mod_val_init = CFG_DDR2_MODE_VAL_INIT;
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mod_val = CFG_DDR2_MODE_VAL;
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tap_val = CFG_DDR2_TAP_VAL;
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cycle_val = CFG_DDR2_RD_DATA_THIS_CYCLE_VAL_16;
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ctl_config = CFG_DDR_CTL_CONFIG | DDR_CTL_CONFIG_PAD_DDR2_SEL_SET(0x1) |
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DDR_CTL_CONFIG_HALF_WIDTH_SET(0x1) | CPU_DDR_SYNC_MODE;
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writel(0x10, ddr_regs + AR71XX_DDR_REG_CONTROL);
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udelay(10);
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writel(0x20, ddr_regs + AR71XX_DDR_REG_CONTROL);
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udelay(10);
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writel(ctl_config, ddr_regs + QCA956X_DDR_REG_CTL_CONF);
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udelay(10);
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writel(cycle_val, ddr_regs + AR71XX_DDR_REG_RD_CYCLE);
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udelay(100);
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writel(0x74444444, ddr_regs + QCA956X_DDR_REG_BURST);
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udelay(100);
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writel(0x44444444, ddr_regs + QCA956X_DDR_REG_BURST2);
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udelay(100);
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writel(DDR_FSM_WAIT_CTRL_VAL, ddr_regs + QCA956X_DDR_REG_FSM_WAIT_CTRL);
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udelay(100);
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writel(0xfffff, ddr_regs + QCA956X_DDR_REG_TIMEOUT_MAX);
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udelay(100);
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writel(ddr_config, ddr_regs + AR71XX_DDR_REG_CONFIG);
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udelay(100);
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writel(ddr_config2, ddr_regs + AR71XX_DDR_REG_CONFIG2);
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udelay(100);
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writel(ddr_config3, ddr_regs + QCA956X_DDR_REG_DDR3_CONFIG);
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udelay(100);
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writel(CFG_DDR2_EN_TWL_VAL, ddr_regs + QCA956X_DDR_REG_DDR2_CONFIG);
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udelay(100);
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writel(ddr_config2 | 0x80, ddr_regs + AR71XX_DDR_REG_CONFIG2); /* CKE Enable */
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udelay(100);
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writel(0x8, ddr_regs + AR71XX_DDR_REG_CONTROL); /* Precharge */
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udelay(10);
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writel(0, ddr_regs + QCA956X_DDR_REG_DDR2_EMR2);
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writel(0x10, ddr_regs + AR71XX_DDR_REG_CONTROL); /* EMR2 */
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udelay(10);
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writel(0, ddr_regs + QCA956X_DDR_REG_DDR2_EMR3);
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writel(0x20, ddr_regs + AR71XX_DDR_REG_CONTROL); /* EMR3 */
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udelay(10);
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/* EMR DLL enable, Reduced Driver Impedance control, Differential DQS disabled */
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writel(CFG_DDR2_EXT_MODE_VAL2, ddr_regs + AR71XX_DDR_REG_EMR);
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udelay(100);
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writel(0x2, ddr_regs + AR71XX_DDR_REG_CONTROL); /* EMR write */
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udelay(10);
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writel(mod_val_init, ddr_regs + AR71XX_DDR_REG_MODE);
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udelay(1000);
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writel(0x1, ddr_regs + AR71XX_DDR_REG_CONTROL); /* MR Write */
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udelay(10);
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writel(0x8, ddr_regs + AR71XX_DDR_REG_CONTROL); /* Precharge */
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udelay(10);
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writel(0x4, ddr_regs + AR71XX_DDR_REG_CONTROL); /* Auto Refresh */
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udelay(10);
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writel(0x4, ddr_regs + AR71XX_DDR_REG_CONTROL); /* Auto Refresh */
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udelay(10);
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/* Issue MRS to remove DLL out-of-reset */
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writel(mod_val, ddr_regs + AR71XX_DDR_REG_MODE);
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udelay(100);
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writel(0x1, ddr_regs + AR71XX_DDR_REG_CONTROL); /* MR write */
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udelay(100);
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writel(CFG_DDR2_EXT_MODE_VAL1, ddr_regs + AR71XX_DDR_REG_EMR);
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udelay(100);
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writel(0x2, ddr_regs + AR71XX_DDR_REG_CONTROL); /* EMR write */
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udelay(100);
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writel(CFG_DDR2_EXT_MODE_VAL2, ddr_regs + AR71XX_DDR_REG_EMR);
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udelay(100);
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writel(0x2, ddr_regs + AR71XX_DDR_REG_CONTROL); /* EMR write */
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udelay(100);
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writel(CFG_DDR2_REFRESH_VAL, ddr_regs + AR71XX_DDR_REG_REFRESH);
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udelay(100);
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writel(tap_val, ddr_regs + AR71XX_DDR_REG_TAP_CTRL0);
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writel(tap_val, ddr_regs + AR71XX_DDR_REG_TAP_CTRL1);
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writel(tap_val, ddr_regs + QCA956X_DDR_REG_TAP_CTRL2);
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writel(tap_val, ddr_regs + QCA956X_DDR_REG_TAP_CTRL3);
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writel(0x633c8176, srif_regs + QCA956X_SRIF_PMU1_REG);
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/* Set DDR2 Voltage to 1.8 volts */
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writel(PMU2_SWREGMSB_SET(0x40) | PMU2_PGM_SET(0x1),
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srif_regs + QCA956X_SRIF_PMU2_REG);
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}
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