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66525bb732
Add support for the ANX9804 bridge chip, which can take pixel data coming from a parallel LCD interface and translate it on the fly into a DP interface for driving eDP TFT displays. It uses I2C for configuration. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Anatolij Gustschin <agust@denx.de>
188 lines
5.6 KiB
C
Executable file
188 lines
5.6 KiB
C
Executable file
/*
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* (C) 2015 Hans de Goede <hdegoede@redhat.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/*
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* Support for the ANX9804 bridge chip, which can take pixel data coming
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* from a parallel LCD interface and translate it on the flight into a DP
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* interface for driving eDP TFT displays.
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*/
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#include <common.h>
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#include <i2c.h>
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#include "anx9804.h"
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#define BIT(x) (1 << (x))
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/* Registers at i2c address 0x38 */
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#define ANX9804_HDCP_CONTROL_0_REG 0x01
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#define ANX9804_SYS_CTRL2_REG 0x81
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#define ANX9804_SYS_CTRL2_CHA_STA 0x04
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#define ANX9804_SYS_CTRL3_REG 0x82
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#define ANX9804_SYS_CTRL3_VALID_CTRL BIT(0)
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#define ANX9804_SYS_CTRL3_F_VALID BIT(1)
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#define ANX9804_SYS_CTRL3_HPD_CTRL BIT(4)
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#define ANX9804_SYS_CTRL3_F_HPD BIT(5)
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#define ANX9804_LINK_BW_SET_REG 0xa0
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#define ANX9804_LANE_COUNT_SET_REG 0xa1
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#define ANX9804_TRAINING_PTN_SET_REG 0xa2
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#define ANX9804_TRAINING_LANE0_SET_REG 0xa3
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#define ANX9804_TRAINING_LANE1_SET_REG 0xa4
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#define ANX9804_TRAINING_LANE2_SET_REG 0xa5
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#define ANX9804_TRAINING_LANE3_SET_REG 0xa6
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#define ANX9804_LINK_TRAINING_CTRL_REG 0xa8
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#define ANX9804_LINK_TRAINING_CTRL_EN BIT(0)
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#define ANX9804_LINK_DEBUG_REG 0xb8
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#define ANX9804_PLL_CTRL_REG 0xc7
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#define ANX9804_ANALOG_POWER_DOWN_REG 0xc8
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/* Registers at i2c address 0x39 */
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#define ANX9804_DEV_IDH_REG 0x03
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#define ANX9804_POWERD_CTRL_REG 0x05
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#define ANX9804_POWERD_AUDIO BIT(4)
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#define ANX9804_RST_CTRL_REG 0x06
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#define ANX9804_RST_CTRL2_REG 0x07
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#define ANX9804_RST_CTRL2_AUX BIT(2)
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#define ANX9804_RST_CTRL2_AC_MODE BIT(6)
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#define ANX9804_VID_CTRL1_REG 0x08
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#define ANX9804_VID_CTRL1_VID_EN BIT(7)
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#define ANX9804_VID_CTRL1_EDGE BIT(0)
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#define ANX9804_VID_CTRL2_REG 0x09
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#define ANX9804_ANALOG_DEBUG_REG1 0xdc
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#define ANX9804_ANALOG_DEBUG_REG3 0xde
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#define ANX9804_PLL_FILTER_CTRL1 0xdf
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#define ANX9804_PLL_FILTER_CTRL3 0xe1
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#define ANX9804_PLL_FILTER_CTRL 0xe2
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#define ANX9804_PLL_CTRL3 0xe6
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/**
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* anx9804_init() - Init anx9804 parallel lcd to edp bridge chip
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*
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* This function will init an anx9804 parallel lcd to dp bridge chip
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* using the passed in parameters.
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*
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* @i2c_bus: Number of the i2c bus to which the anx9804 is connected.
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* @lanes: Number of displayport lanes to use
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* @data_rate: Register value for the bandwidth reg 0x06: 1.62G, 0x0a: 2.7G
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* @bpp: Bits per pixel, must be 18 or 24
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*/
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void anx9804_init(unsigned int i2c_bus, u8 lanes, u8 data_rate, int bpp)
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{
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unsigned int orig_i2c_bus = i2c_get_bus_num();
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u8 c, colordepth;
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int i;
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i2c_set_bus_num(i2c_bus);
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if (bpp == 18)
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colordepth = 0x00; /* 6 bit */
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else
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colordepth = 0x10; /* 8 bit */
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/* Reset */
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i2c_reg_write(0x39, ANX9804_RST_CTRL_REG, 1);
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mdelay(100);
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i2c_reg_write(0x39, ANX9804_RST_CTRL_REG, 0);
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/* Write 0 to the powerdown reg (powerup everything) */
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i2c_reg_write(0x39, ANX9804_POWERD_CTRL_REG, 0);
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c = i2c_reg_read(0x39, ANX9804_DEV_IDH_REG);
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if (c != 0x98) {
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printf("Error anx9804 chipid mismatch\n");
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i2c_set_bus_num(orig_i2c_bus);
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return;
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}
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for (i = 0; i < 100; i++) {
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c = i2c_reg_read(0x38, ANX9804_SYS_CTRL2_REG);
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i2c_reg_write(0x38, ANX9804_SYS_CTRL2_REG, c);
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c = i2c_reg_read(0x38, ANX9804_SYS_CTRL2_REG);
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if ((c & ANX9804_SYS_CTRL2_CHA_STA) == 0)
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break;
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mdelay(5);
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}
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if (i == 100)
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printf("Error anx9804 clock is not stable\n");
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i2c_reg_write(0x39, ANX9804_VID_CTRL2_REG, colordepth);
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/* Set a bunch of analog related register values */
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i2c_reg_write(0x38, ANX9804_PLL_CTRL_REG, 0x07);
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i2c_reg_write(0x39, ANX9804_PLL_FILTER_CTRL3, 0x19);
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i2c_reg_write(0x39, ANX9804_PLL_CTRL3, 0xd9);
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i2c_reg_write(0x39, ANX9804_RST_CTRL2_REG, ANX9804_RST_CTRL2_AC_MODE);
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i2c_reg_write(0x39, ANX9804_ANALOG_DEBUG_REG1, 0xf0);
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i2c_reg_write(0x39, ANX9804_ANALOG_DEBUG_REG3, 0x99);
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i2c_reg_write(0x39, ANX9804_PLL_FILTER_CTRL1, 0x7b);
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i2c_reg_write(0x38, ANX9804_LINK_DEBUG_REG, 0x30);
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i2c_reg_write(0x39, ANX9804_PLL_FILTER_CTRL, 0x06);
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/* Force HPD */
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i2c_reg_write(0x38, ANX9804_SYS_CTRL3_REG,
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ANX9804_SYS_CTRL3_F_HPD | ANX9804_SYS_CTRL3_HPD_CTRL);
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/* Power up and configure lanes */
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i2c_reg_write(0x38, ANX9804_ANALOG_POWER_DOWN_REG, 0x00);
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i2c_reg_write(0x38, ANX9804_TRAINING_LANE0_SET_REG, 0x00);
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i2c_reg_write(0x38, ANX9804_TRAINING_LANE1_SET_REG, 0x00);
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i2c_reg_write(0x38, ANX9804_TRAINING_LANE2_SET_REG, 0x00);
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i2c_reg_write(0x38, ANX9804_TRAINING_LANE3_SET_REG, 0x00);
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/* Reset AUX CH */
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i2c_reg_write(0x39, ANX9804_RST_CTRL2_REG,
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ANX9804_RST_CTRL2_AC_MODE | ANX9804_RST_CTRL2_AUX);
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i2c_reg_write(0x39, ANX9804_RST_CTRL2_REG,
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ANX9804_RST_CTRL2_AC_MODE);
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/* Powerdown audio and some other unused bits */
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i2c_reg_write(0x39, ANX9804_POWERD_CTRL_REG, ANX9804_POWERD_AUDIO);
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i2c_reg_write(0x38, ANX9804_HDCP_CONTROL_0_REG, 0x00);
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i2c_reg_write(0x38, 0xa7, 0x00);
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/* Set data-rate / lanes */
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i2c_reg_write(0x38, ANX9804_LINK_BW_SET_REG, data_rate);
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i2c_reg_write(0x38, ANX9804_LANE_COUNT_SET_REG, lanes);
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/* Link training */
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i2c_reg_write(0x38, ANX9804_LINK_TRAINING_CTRL_REG,
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ANX9804_LINK_TRAINING_CTRL_EN);
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mdelay(5);
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for (i = 0; i < 100; i++) {
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c = i2c_reg_read(0x38, ANX9804_LINK_TRAINING_CTRL_REG);
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if ((c & 0x01) == 0)
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break;
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mdelay(5);
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}
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if(i == 100) {
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printf("Error anx9804 link training timeout\n");
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i2c_set_bus_num(orig_i2c_bus);
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return;
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}
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/* Enable */
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i2c_reg_write(0x39, ANX9804_VID_CTRL1_REG,
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ANX9804_VID_CTRL1_VID_EN | ANX9804_VID_CTRL1_EDGE);
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/* Force stream valid */
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i2c_reg_write(0x38, ANX9804_SYS_CTRL3_REG,
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ANX9804_SYS_CTRL3_F_HPD | ANX9804_SYS_CTRL3_HPD_CTRL |
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ANX9804_SYS_CTRL3_F_VALID | ANX9804_SYS_CTRL3_VALID_CTRL);
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i2c_set_bus_num(orig_i2c_bus);
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}
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