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2d481b2e3e
This adds the driver for the PWM controller found in the Amlogic SoCs. This PWM is only a set of Gates, Dividers and Counters: PWM output is achieved by calculating a clock that permits calculating two periods (low and high). The counter then has to be set to switch after N cycles for the first half period. The hardware has no "polarity" setting. This driver reverses the period cycles (the low length is inverted with the high length) for PWM_POLARITY_INVERSED. Disabling the PWM stops the output immediately (without waiting for the current period to complete first). Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> |
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.. | ||
exynos_pwm.c | ||
Kconfig | ||
Makefile | ||
pwm-imx-util.c | ||
pwm-imx-util.h | ||
pwm-imx.c | ||
pwm-meson.c | ||
pwm-mtk.c | ||
pwm-sifive.c | ||
pwm-uclass.c | ||
rk_pwm.c | ||
sandbox_pwm.c | ||
sunxi_pwm.c | ||
tegra_pwm.c |