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https://github.com/AsahiLinux/u-boot
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80885a9d52
NS9750 DevBoard added * Patch by Pierre AUBERT, 24 Feb 2004 add USB support for MPC5200 * Patch by Steven Scholz, 24 Feb 2004: - fix MII commands to use values from last command * Patch by Torsten Demke, 24 Feb 2004: Add support for the eXalion platform (SPSW-8240, F-30, F-300)
202 lines
7.8 KiB
C
202 lines
7.8 KiB
C
/***********************************************************************
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*
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* Copyright (C) 2004 by FS Forth-Systeme GmbH.
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* All rights reserved.
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*
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* $Id: ns9750_ser.h,v 1.1 2004/02/16 10:37:20 mpietrek Exp $
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* @Author: Markus Pietrek
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* @References: [1] NS9750 Hardware Reference, December 2003
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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***********************************************************************/
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#ifndef FS_NS9750_SER_H
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#define FS_NS9750_SER_H
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#define NS9750_SER_MODULE_BASE (0x90200000)
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#define get_ser_reg_addr(c) \
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((volatile unsigned int *)(NS9750_SER_MODULE_BASE+(unsigned int) (c)))
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#define get_ser_reg_addr_channel(reg,chan) \
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get_ser_reg_addr((reg)+(((chan)<2)?0:0x00100000)+(((chan)&1)?0x40:0))
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/* the register addresses */
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#define NS9750_SER_CTRL_A (0x00)
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#define NS9750_SER_CTRL_B (0x04)
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#define NS9750_SER_STAT_A (0x08)
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#define NS9750_SER_BITRATE (0x0C)
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#define NS9750_SER_FIFO (0x10)
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#define NS9750_SER_RX_BUF_TIMER (0x14)
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#define NS9750_SER_RX_CHAR_TIMER (0x18)
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#define NS9750_SER_RX_MATCH (0x1C)
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#define NS9750_SER_RX_MATCH_MASK (0x20)
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#define NS9750_SER_FLOW_CTRL (0x34)
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#define NS9750_SER_FLOW_CTRL_FORCE (0x38)
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/* register bit fields */
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/* control A register */
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#define NS9750_SER_CTRL_A_CE (0x80000000)
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#define NS9750_SER_CTRL_A_BRK (0x40000000)
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#define NS9750_SER_CTRL_A_STICKP (0x20000000)
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#define NS9750_SER_CTRL_A_EPS (0x10000000)
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#define NS9750_SER_CTRL_A_PE (0x08000000)
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#define NS9750_SER_CTRL_A_STOP (0x04000000)
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#define NS9750_SER_CTRL_A_WLS_MA (0x03000000)
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#define NS9750_SER_CTRL_A_WLS_5 (0x00000000)
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#define NS9750_SER_CTRL_A_WLS_6 (0x01000000)
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#define NS9750_SER_CTRL_A_WLS_7 (0x02000000)
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#define NS9750_SER_CTRL_A_WLS_8 (0x03000000)
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#define NS9750_SER_CTRL_A_CTSTX (0x00800000)
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#define NS9750_SER_CTRL_A_RTSRX (0x00400000)
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#define NS9750_SER_CTRL_A_RL (0x00200000)
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#define NS9750_SER_CTRL_A_LL (0x00100000)
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#define NS9750_SER_CTRL_A_RES (0x000CF000)
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#define NS9750_SER_CTRL_A_DTR (0x00020000)
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#define NS9750_SER_CTRL_A_RTS (0x00010000)
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#define NS9750_SER_CTRL_A_RIE_MA (0x00000E00)
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#define NS9750_SER_CTRL_A_ERXDMA (0x00000100)
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#define NS9750_SER_CTRL_A_RIC_MA (0x000000E0)
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#define NS9750_SER_CTRL_A_TIC_MA (0x0000001E)
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#define NS9750_SER_CTRL_A_ETXDMA (0x00000001)
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/* control B register */
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#define NS9750_SER_CTRL_B_RDM1 (0x80000000)
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#define NS9750_SER_CTRL_B_RDM2 (0x40000000)
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#define NS9750_SER_CTRL_B_RDM3 (0x20000000)
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#define NS9750_SER_CTRL_B_RDM4 (0x10000000)
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#define NS9750_SER_CTRL_B_RBGT (0x08000000)
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#define NS9750_SER_CTRL_B_RCGT (0x04000000)
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#define NS9750_SER_CTRL_B_MODE_MA (0x00300000)
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#define NS9750_SER_CTRL_B_MODE_UART (0x00000000)
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#define NS9750_SER_CTRL_B_MODE_HDLC (0x00100000)
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#define NS9750_SER_CTRL_B_MODE_SPI_M (0x00200000)
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#define NS9750_SER_CTRL_B_MODE_SPI_S (0x00300000)
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#define NS9750_SER_CTRL_B_BITORDR (0x00080000)
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#define NS9750_SER_CTRL_B_RES (0x0007703F)
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#define NS9750_SER_CTRL_B_RTSTX (0x00008000)
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#define NS9750_SER_CTRL_B_ENDEC_MA (0x00000FC0)
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/* status A register */
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#define NS9750_SER_STAT_A_MATCH1 (0x80000000)
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#define NS9750_SER_STAT_A_MATCH2 (0x40000000)
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#define NS9750_SER_STAT_A_MATCH3 (0x20000000)
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#define NS9750_SER_STAT_A_MATCH4 (0x10000000)
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#define NS9750_SER_STAT_A_BGAP (0x08000000)
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#define NS9750_SER_STAT_A_CGAP (0x04000000)
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#define NS9750_SER_STAT_A_RXFDB_MA (0x00300000)
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#define NS9750_SER_STAT_A_RXFDB_FULL (0x00000000)
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#define NS9750_SER_STAT_A_RXFDB_1 (0x00100000)
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#define NS9750_SER_STAT_A_RXFDB_2 (0x00200000)
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#define NS9750_SER_STAT_A_RXFDB_3 (0x00300000)
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#define NS9750_SER_STAT_A_DCD (0x00080000)
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#define NS9750_SER_STAT_A_RI (0x00040000)
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#define NS9750_SER_STAT_A_DSR (0x00020000)
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#define NS9750_SER_STAT_A_CTS (0x00010000)
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#define NS9750_SER_STAT_A_RBRK (0x00008000)
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#define NS9750_SER_STAT_A_RFE (0x00004000)
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#define NS9750_SER_STAT_A_RPE (0x00002000)
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#define NS9750_SER_STAT_A_ROVER (0x00001000)
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#define NS9750_SER_STAT_A_RRDY (0x00000800)
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#define NS9750_SER_STAT_A_RHALF (0x00000400)
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#define NS9750_SER_STAT_A_RBC (0x00000200)
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#define NS9750_SER_STAT_A_RFULL (0x00000100)
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#define NS9750_SER_STAT_A_DCDI (0x00000080)
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#define NS9750_SER_STAT_A_RII (0x00000040)
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#define NS9750_SER_STAT_A_DSRI (0x00000020)
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#define NS9750_SER_STAT_A_CTSI (0x00000010)
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#define NS9750_SER_STAT_A_TRDY (0x00000008)
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#define NS9750_SER_STAT_A_THALF (0x00000004)
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#define NS9750_SER_STAT_A_TBC (0x00000002)
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#define NS9750_SER_STAT_A_TEMPTY (0x00000001)
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#define NS9750_SER_STAT_A_RX_COND_ERR ( NS9750_SER_STAT_A_RFE | \
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NS9750_SER_STAT_A_ROVER | \
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NS9750_SER_STAT_A_RPE )
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#define NS9750_SER_STAT_A_RX_COND_ALL ( NS9750_SER_STAT_A_RX_COND_ERR | \
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NS9750_SER_STAT_A_RBRK | \
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NS9750_SER_STAT_A_RRDY | \
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NS9750_SER_STAT_A_RHALF | \
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NS9750_SER_STAT_A_RBC | \
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NS9750_SER_STAT_A_DCDI | \
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NS9750_SER_STAT_A_RII | \
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NS9750_SER_STAT_A_DSRI | \
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NS9750_SER_STAT_A_CTSI )
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#define NS9750_SER_STAT_A_TX_COND_ALL ( NS9750_SER_STAT_A_TRDY | \
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NS9750_SER_STAT_A_THALF | \
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NS9750_SER_STAT_A_TBC | \
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NS9750_SER_STAT_A_TEMPTY )
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/* bit rate register */
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#define NS9750_SER_BITRATE_EBIT (0x80000000)
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#define NS9750_SER_BITRATE_TMODE (0x40000000)
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#define NS9750_SER_BITRATE_RXSRC (0x20000000)
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#define NS9750_SER_BITRATE_TXSRC (0x10000000)
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#define NS9750_SER_BITRATE_RXEXT (0x08000000)
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#define NS9750_SER_BITRATE_TXEXT (0x04000000)
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#define NS9750_SER_BITRATE_CLKMUX_MA (0x03000000)
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#define NS9750_SER_BITRATE_CLKMUX_XTAL (0x00000000)
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#define NS9750_SER_BITRATE_CLKMUX_BCLK (0x01000000)
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#define NS9750_SER_BITRATE_CLKMUX_OUT1 (0x02000000)
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#define NS9750_SER_BITRATE_CLKMUX_OUT2 (0x03000000)
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#define NS9750_SER_BITRATE_TXCINV (0x00800000)
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#define NS9750_SER_BITRATE_RXCINV (0x00400000)
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#define NS9750_SER_BITRATE_TCDR_MA (0x00180000)
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#define NS9750_SER_BITRATE_TCDR_1 (0x00000000)
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#define NS9750_SER_BITRATE_TCDR_8 (0x00080000)
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#define NS9750_SER_BITRATE_TCDR_16 (0x00100000)
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#define NS9750_SER_BITRATE_TCDR_32 (0x00180000)
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#define NS9750_SER_BITRATE_RCDR_MA (0x00070000)
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#define NS9750_SER_BITRATE_RCDR_1 (0x00000000)
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#define NS9750_SER_BITRATE_RCDR_8 (0x00020000)
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#define NS9750_SER_BITRATE_RCDR_16 (0x00040000)
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#define NS9750_SER_BITRATE_RCDR_32 (0x00060000)
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#define NS9750_SER_BITRATE_TICS (0x00010000)
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#define NS9750_SER_BITRATE_RICS (0x00008000)
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#define NS9750_SER_BITRATE_N_MA (0x00007FFF)
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/* receive buffer gap timer */
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#define NS9750_SER_RX_BUF_TIMER_TRUN (0x80000000) /* UART and SPI */
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#define NS9750_SER_RX_BUF_TIMER_BT_MA (0x0000FFFF) /* UART and SPI */
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#define NS9750_SER_RX_BUF_TIMER_MAXLEN_MA (0x0000FFFF) /* HDLC only */
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/* receive character gap timer */
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#define NS9750_SER_RX_CHAR_TIMER_TRUN (0x80000000)
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#define NS9750_SER_RX_CHAR_TIMER_CT_MA (0x000FFFFF)
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/* receive match */
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#define NS9750_SER_RX_MATCH_RDMB1_MA (0xFF000000)
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#define NS9750_SER_RX_MATCH_RDMB2_MA (0x00FF0000)
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#define NS9750_SER_RX_MATCH_RDMB3_MA (0x0000FF00)
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#define NS9750_SER_RX_MATCH_RDMB4_MA (0x000000FF)
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/* receive match mask */
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#define NS9750_SER_RX_MATCH_MASK_RDMB1_MA (0xFF000000)
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#define NS9750_SER_RX_MATCH_MASK_RDMB2_MA (0x00FF0000)
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#define NS9750_SER_RX_MATCH_MASK_RDMB3_MA (0x0000FF00)
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#define NS9750_SER_RX_MATCH_MASK_RDMB4_MA (0x000000FF)
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#endif /* FS_NS9750_SER_H */
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