mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-11 15:37:23 +00:00
9c4c5ae3e1
- Convert the CPM2 based functionality to use new CONFIG_CPM2
option rather than a myriad of CONFIG_MPC8560-like variants.
Applies to MPC85xx and MPC8260 boards, includes stxgp3 and sbc8560.
Eliminates the CONFIG_MPC8560 option entirely. Distributes the
new CONFIG_CPM2 option to each 8260 board.
418 lines
14 KiB
C
418 lines
14 KiB
C
/*
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* (C) Copyright 2000
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* Murray Jensen <Murray.Jensen@cmst.csiro.au>
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*
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* (C) Copyright 2000
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
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* Marius Groeger <mgroeger@sysgo.de>
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*
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* Configuation settings for the R&S Protocol Board board.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* High Level Configuration Options
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* (easy to change)
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*/
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#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */
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#define CONFIG_RSD_PROTO 1 /* on a R&S Protocol Board */
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#define CONFIG_CPM2 1 /* Has a CPM2 */
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#define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */
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/*
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* select serial console configuration
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*
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* if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
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* CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
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* for SCC).
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*
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* if CONFIG_CONS_NONE is defined, then the serial console routines must
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* defined elsewhere.
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*/
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#undef CONFIG_CONS_ON_SMC /* define if console on SMC */
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#define CONFIG_CONS_ON_SCC /* define if console on SCC */
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#undef CONFIG_CONS_NONE /* define if console on neither */
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#define CONFIG_CONS_INDEX 1 /* which SMC/SCC channel for console */
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/*
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* select ethernet configuration
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*
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* if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
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* CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
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* for FCC)
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*
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* if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
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* defined elsewhere (as for the console), or CFG_CMD_NET must be removed
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* from CONFIG_COMMANDS to remove support for networking.
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*/
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#undef CONFIG_ETHER_ON_SCC /* define if ethernet on SCC */
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#define CONFIG_ETHER_ON_FCC /* define if ethernet on FCC */
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#undef CONFIG_ETHER_NONE /* define if ethernet on neither */
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#define CONFIG_ETHER_INDEX 2 /* which SCC/FCC channel for ethernet */
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#if (CONFIG_ETHER_INDEX == 2)
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/*
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* - Rx-CLK is CLK13
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* - Tx-CLK is CLK14
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* - Select bus for bd/buffers (see 28-13)
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* - Enable Full Duplex in FSMR
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*/
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# define CFG_CMXFCR_MASK (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
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# define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
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# define CFG_CPMFCR_RAMTYPE (0)
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# define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
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#endif /* CONFIG_ETHER_INDEX */
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/* allow to overwrite serial and ethaddr */
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#define CONFIG_ENV_OVERWRITE
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/* enable I2C */
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#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
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#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
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#define CFG_I2C_SLAVE 0x7F
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/* system clock rate (CLKIN) - equal to the 60x and local bus speed */
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#define CONFIG_8260_CLKIN 50000000 /* in Hz */
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#define CONFIG_BAUDRATE 115200
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#define CONFIG_COMMANDS (CONFIG_CMD_DFL & ~CFG_CMD_KGDB)
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/* Define this if you want to boot from 0x00000100. If you don't define
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* this, you will need to program the bootloader to 0xfff00000, and
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* get the hardware reset config words at 0xfe000000. The simplest
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* way to do that is to program the bootloader at both addresses.
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* It is suggested that you just let U-Boot live at 0x00000000.
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*/
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#define CFG_RSD_BOOT_LOW 1
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/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
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#include <cmd_confdefs.h>
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#define CONFIG_BOOTDELAY 5
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#define CONFIG_BOOTARGS "devfs=mount root=ramfs"
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#define CONFIG_ETHADDR 08:00:3e:26:0a:5a
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#define CONFIG_NETMASK 255.255.0.0
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#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
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#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
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#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
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#endif
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/*
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* Miscellaneous configurable options
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*/
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#define CFG_LONGHELP /* undef to save memory */
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#define CFG_PROMPT "=> " /* Monitor Command Prompt */
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#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
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#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
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#else
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#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
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#endif
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#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
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#define CFG_MAXARGS 16 /* max number of command args */
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#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
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#define CFG_MEMTEST_START 0x00400000 /* memtest works on */
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#define CFG_MEMTEST_END 0x01c00000 /* 4 ... 28 MB in DRAM */
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#define CFG_LOAD_ADDR 0x100000 /* default load address */
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#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
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/* valid baudrates */
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#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
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/*
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* Low Level Configuration Settings
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* (address mappings, register initial values, etc.)
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* You should know what you are doing if you make changes here.
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*/
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/*-----------------------------------------------------------------------
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* Physical Memory Map
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*/
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#define PHYS_SDRAM_60X 0x00000000 /* SDRAM (60x Bus) */
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#define PHYS_SDRAM_60X_SIZE 0x08000000 /* 128 MB */
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#define PHYS_SDRAM_LOCAL 0x40000000 /* SDRAM (Local Bus) */
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#define PHYS_SDRAM_LOCAL_SIZE 0x04000000 /* 64 MB */
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#define PHYS_DPRAM_PCI 0xE8000000 /* DPRAM PPC/PCI */
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#define PHYS_DPRAM_PCI_SIZE 0x00020000 /* 128 KB */
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/*#define PHYS_DPRAM_PCI_SEM 0x04020000 / * DPRAM PPC/PCI Semaphore */
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/*#define PHYS_DPRAM_PCI_SEM_SIZE 0x00000001 / * 1 Byte */
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#define PHYS_DPRAM_SHARC 0xE8100000 /* DPRAM PPC/Sharc */
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#define PHYS_DPRAM_SHARC_SIZE 0x00040000 /* 256 KB */
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/*#define PHYS_DPRAM_SHARC_SEM 0x04140000 / * DPRAM PPC/Sharc Semaphore */
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/*#define PHYS_DPRAM_SHARC_SEM_SIZE 0x00000001 / * 1 Byte */
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#define PHYS_VIRTEX_REGISTER 0xE8300000 /* FPGA implemented register */
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#define PHYS_VIRTEX_REGISTER_SIZE 0x00000100
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#define PHYS_USB 0x04200000 /* USB Controller (60x Bus) */
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#define PHYS_USB_SIZE 0x00000002 /* 2 Bytes */
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#define PHYS_IMMR 0xF0000000 /* Internal Memory Mapped Reg. */
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#define PHYS_FLASH 0xFF000000 /* Flash (60x Bus) */
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#define PHYS_FLASH_SIZE 0x01000000 /* 16 MB */
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#define CFG_IMMR PHYS_IMMR
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/*-----------------------------------------------------------------------
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* Reset Address
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*
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* In order to reset the CPU, U-Boot jumps to a special address which
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* causes a machine check exception. The default address for this is
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* CFG_MONITOR_BASE - sizeof (ulong), which might not always work, eg. when
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* testing the monitor in RAM using a JTAG debugger.
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*
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* Just set CFG_RESET_ADDRESS to an address that you know is sure to
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* cause a bus error on your hardware.
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*/
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#define CFG_RESET_ADDRESS 0x20000000
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/*-----------------------------------------------------------------------
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* Hard Reset Configuration Words
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*/
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#if defined(CFG_RSD_BOOT_LOW)
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# define CFG_RSD_HRCW_BOOT_FLAGS (HRCW_CIP | HRCW_BMS)
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#else
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# define CFG_RSD_HRCW_BOOT_FLAGS (0)
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#endif /* defined(CFG_RSD_BOOT_LOW) */
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/* get the HRCW ISB field from CFG_IMMR */
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#define CFG_RSD_HRCW_IMMR ( ((CFG_IMMR & 0x10000000) >> 10) |\
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((CFG_IMMR & 0x01000000) >> 7) |\
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((CFG_IMMR & 0x00100000) >> 4) )
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#define CFG_HRCW_MASTER (HRCW_L2CPC10 | \
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HRCW_DPPC11 | \
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CFG_RSD_HRCW_IMMR |\
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HRCW_MMR00 | \
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HRCW_APPC10 | \
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HRCW_CS10PC00 | \
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HRCW_MODCK_H0000 |\
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CFG_RSD_HRCW_BOOT_FLAGS)
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/* no slaves */
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#define CFG_HRCW_SLAVE1 0
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#define CFG_HRCW_SLAVE2 0
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#define CFG_HRCW_SLAVE3 0
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#define CFG_HRCW_SLAVE4 0
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#define CFG_HRCW_SLAVE5 0
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#define CFG_HRCW_SLAVE6 0
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#define CFG_HRCW_SLAVE7 0
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/*-----------------------------------------------------------------------
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* Definitions for initial stack pointer and data area (in DPRAM)
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*/
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#define CFG_INIT_RAM_ADDR CFG_IMMR
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#define CFG_INIT_RAM_END 0x4000 /* End of used area in DPRAM */
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#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
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#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
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#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
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/*-----------------------------------------------------------------------
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* Start addresses for the final memory configuration
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* (Set up by the startup code)
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* Please note that CFG_SDRAM_BASE _must_ start at 0
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* Note also that the logic that sets CFG_RAMBOOT is platform dependend.
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*/
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#define CFG_SDRAM_BASE PHYS_SDRAM_60X
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#define CFG_FLASH_BASE PHYS_FLASH
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/*#define CFG_MONITOR_BASE 0x200000 */
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#define CFG_MONITOR_BASE CFG_FLASH_BASE
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#if CFG_MONITOR_BASE < CFG_FLASH_BASE
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#define CFG_RAMBOOT
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#endif
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#define CFG_MONITOR_LEN (160 << 10) /* Reserve 160 kB for Monitor */
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#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 8 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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*/
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#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
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/*-----------------------------------------------------------------------
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* FLASH and environment organization
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*/
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#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
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#define CFG_MAX_FLASH_SECT 63 /* max number of sectors on one chip */
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#define CFG_FLASH_ERASE_TOUT 12000 /* Timeout for Flash Erase (in ms) */
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#define CFG_FLASH_WRITE_TOUT 3000 /* Timeout for Flash Write (in ms) */
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/* turn off NVRAM env feature */
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#undef CONFIG_NVRAM_ENV
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#define CFG_ENV_IS_IN_FLASH 1
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#define CFG_ENV_ADDR (PHYS_FLASH + 0x28000) /* Addr of Environment Sector */
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#define CFG_ENV_SECT_SIZE 0x8000 /* Total Size of Environment Sector */
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/*-----------------------------------------------------------------------
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* Cache Configuration
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*/
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#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */
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#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
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#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
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#endif
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/*-----------------------------------------------------------------------
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* HIDx - Hardware Implementation-dependent Registers 2-11
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*-----------------------------------------------------------------------
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* HID0 also contains cache control - initially enable both caches and
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* invalidate contents, then the final state leaves only the instruction
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* cache enabled. Note that Power-On and Hard reset invalidate the caches,
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* but Soft reset does not.
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*
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* HID1 has only read-only information - nothing to set.
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*/
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#define CFG_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|HID0_IFEM|HID0_ABE)
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#define CFG_HID0_FINAL (HID0_ICE|HID0_IFEM|HID0_ABE|HID0_EMCP)
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#define CFG_HID2 0
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/*-----------------------------------------------------------------------
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* RMR - Reset Mode Register
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*-----------------------------------------------------------------------
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*/
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#define CFG_RMR 0
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/*-----------------------------------------------------------------------
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* BCR - Bus Configuration 4-25
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*-----------------------------------------------------------------------
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*/
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#define CFG_BCR 0x100c0000
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/*-----------------------------------------------------------------------
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* SIUMCR - SIU Module Configuration 4-31
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*-----------------------------------------------------------------------
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*/
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#define CFG_SIUMCR (SIUMCR_DPPC11 | SIUMCR_L2CPC10 | SIUMCR_APPC10 | \
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SIUMCR_CS10PC01 | SIUMCR_BCTLC01)
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/*-----------------------------------------------------------------------
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* SYPCR - System Protection Control 11-9
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* SYPCR can only be written once after reset!
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*-----------------------------------------------------------------------
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* Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
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*/
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#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_PBME | SYPCR_LBME | \
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SYPCR_SWRI | SYPCR_SWP)
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/*-----------------------------------------------------------------------
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* TMCNTSC - Time Counter Status and Control 4-40
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*-----------------------------------------------------------------------
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* Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
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* and enable Time Counter
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*/
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#define CFG_TMCNTSC (TMCNTSC_SEC | TMCNTSC_ALR | TMCNTSC_TCF | TMCNTSC_TCE)
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/*-----------------------------------------------------------------------
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* PISCR - Periodic Interrupt Status and Control 4-42
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*-----------------------------------------------------------------------
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* Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
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* Periodic timer
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*/
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#define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
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/*-----------------------------------------------------------------------
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* SCCR - System Clock Control 9-8
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*-----------------------------------------------------------------------
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*/
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#define CFG_SCCR 0x00000000
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/*-----------------------------------------------------------------------
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* RCCR - RISC Controller Configuration 13-7
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*-----------------------------------------------------------------------
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*/
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#define CFG_RCCR 0
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/*
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* Init Memory Controller:
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*/
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#define CFG_PSDMR 0x494D2452
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#define CFG_LSDMR 0x49492552
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/* Flash */
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#define CFG_BR0_PRELIM (PHYS_FLASH | BRx_V)
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#define CFG_OR0_PRELIM (P2SZ_TO_AM(PHYS_FLASH_SIZE) | \
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ORxG_BCTLD | \
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ORxG_SCY_5_CLK)
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/* DPRAM to the PCI BUS on the protocol board */
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#define CFG_BR1_PRELIM (PHYS_DPRAM_PCI | BRx_V)
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#define CFG_OR1_PRELIM (P2SZ_TO_AM(PHYS_DPRAM_PCI_SIZE) | \
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ORxG_ACS_DIV4)
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/* 60x Bus SDRAM */
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#define CFG_BR2_PRELIM (PHYS_SDRAM_60X | BRx_MS_SDRAM_P | BRx_V)
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#define CFG_OR2_PRELIM (ORxS_SIZE_TO_AM(PHYS_SDRAM_60X_SIZE) | \
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ORxS_BPD_4 | \
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ORxS_ROWST_PBI1_A2 | \
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ORxS_NUMR_13 | \
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ORxS_IBID)
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/* Virtex-FPGA - Register */
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#define CFG_BR3_PRELIM (PHYS_VIRTEX_REGISTER | BRx_V)
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#define CFG_OR3_PRELIM (ORxS_SIZE_TO_AM(PHYS_VIRTEX_REGISTER_SIZE) | \
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ORxG_SCY_1_CLK | \
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ORxG_ACS_DIV2 | \
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ORxG_CSNT )
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/* local bus SDRAM */
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#define CFG_BR4_PRELIM (PHYS_SDRAM_LOCAL | BRx_PS_32 | BRx_MS_SDRAM_L | BRx_V)
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#define CFG_OR4_PRELIM (ORxS_SIZE_TO_AM(PHYS_SDRAM_LOCAL_SIZE) | \
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ORxS_BPD_4 | \
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ORxS_ROWST_PBI1_A4 | \
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ORxS_NUMR_13)
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/* DPRAM to the Sharc-Bus on the protocol board */
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#define CFG_BR5_PRELIM (PHYS_DPRAM_SHARC | BRx_V)
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#define CFG_OR5_PRELIM (P2SZ_TO_AM(PHYS_DPRAM_SHARC_SIZE) | \
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ORxG_ACS_DIV4)
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/*
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* Internal Definitions
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*
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* Boot Flags
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*/
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#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
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#define BOOTFLAG_WARM 0x02 /* Software reboot */
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#endif /* __CONFIG_H */
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