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4024006e52
This adds a document for tphy which supports physical layer functionality for a number of controllers on MediaTek SoCs, such as, USB2.0, USB3.0, PCIe, and SATA. Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
86 lines
2.6 KiB
Text
86 lines
2.6 KiB
Text
MediaTek T-PHY binding
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--------------------------
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T-phy controller supports physical layer functionality for a number of
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controllers on MediaTek SoCs, such as, USB2.0, USB3.0, PCIe, and SATA.
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Required properties (controller (parent) node):
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- compatible : should be one of
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"mediatek,generic-tphy-v1"
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- clocks : (deprecated, use port's clocks instead) a list of phandle +
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clock-specifier pairs, one for each entry in clock-names
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- clock-names : (deprecated, use port's one instead) must contain
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"u3phya_ref": for reference clock of usb3.0 analog phy.
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Required nodes : a sub-node is required for each port the controller
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provides. Address range information including the usual
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'reg' property is used inside these nodes to describe
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the controller's topology.
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Optional properties (controller (parent) node):
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- reg : offset and length of register shared by multiple ports,
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exclude port's private register.
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- mediatek,src-ref-clk-mhz : frequency of reference clock for slew rate
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calibrate
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- mediatek,src-coef : coefficient for slew rate calibrate, depends on
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SoC process
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Required properties (port (child) node):
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- reg : address and length of the register set for the port.
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- clocks : a list of phandle + clock-specifier pairs, one for each
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entry in clock-names
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- clock-names : must contain
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"ref": 48M reference clock for HighSpeed analog phy; and 26M
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reference clock for SuperSpeed analog phy, sometimes is
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24M, 25M or 27M, depended on platform.
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- #phy-cells : should be 1 (See second example)
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cell after port phandle is phy type from:
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- PHY_TYPE_USB2
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- PHY_TYPE_USB3
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- PHY_TYPE_PCIE
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- PHY_TYPE_SATA
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Example:
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u3phy2: usb-phy@1a244000 {
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compatible = "mediatek,generic-tphy-v1";
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reg = <0x1a244000 0x0700>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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status = "disabled";
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u2port1: usb-phy@1a244800 {
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reg = <0x1a244800 0x0100>;
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clocks = <&topckgen CLK_TOP_USB_PHY48M>;
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clock-names = "ref";
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#phy-cells = <1>;
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status = "okay";
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};
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u3port1: usb-phy@1a244900 {
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reg = <0x1a244900 0x0700>;
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clocks = <&clk26m>;
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clock-names = "ref";
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#phy-cells = <1>;
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status = "okay";
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};
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};
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Specifying phy control of devices
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---------------------------------
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Device nodes should specify the configuration required in their "phys"
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property, containing a phandle to the phy port node and a device type;
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phy-names for each port are optional.
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Example:
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#include <dt-bindings/phy/phy.h>
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usb30: usb@11270000 {
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...
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phys = <&u2port0 PHY_TYPE_USB2>, <&u3port0 PHY_TYPE_USB3>;
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phy-names = "usb2-0", "usb3-0";
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...
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};
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