mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-04 18:41:03 +00:00
dc5be508b0
Intel IvyBridge FSP seems to be buggy that it does not report memory used by FSP itself as reserved in the resource descriptor HOB. The FSP specification does not describe how resource descriptor HOBs are generated by the FSP to describe what memory regions. It looks newer FSPs like Queensbay and BayTrail do not have such issue. This causes U-Boot relocation overwrites the important boot service data which is used by FSP, and the subsequent call to fsp_notify() will fail. To resolve this, we find out the lowest memory base address allocated by FSP for the boot service data when walking through the HOB list in fsp_get_usable_lowmem_top(). Check whether the memory top address is below the FSP HOB list, and if not, use the lowest memory base address allocated by FSP as the memory top address. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested on link (ivybridge non-FSP) Tested-by: Simon Glass <sjg@chromium.org>
454 lines
13 KiB
Text
454 lines
13 KiB
Text
menu "x86 architecture"
|
|
depends on X86
|
|
|
|
config SYS_ARCH
|
|
default "x86"
|
|
|
|
choice
|
|
prompt "Mainboard vendor"
|
|
default VENDOR_EMULATION
|
|
|
|
config VENDOR_COREBOOT
|
|
bool "coreboot"
|
|
|
|
config VENDOR_EFI
|
|
bool "efi"
|
|
|
|
config VENDOR_EMULATION
|
|
bool "emulation"
|
|
|
|
config VENDOR_GOOGLE
|
|
bool "Google"
|
|
|
|
config VENDOR_INTEL
|
|
bool "Intel"
|
|
|
|
endchoice
|
|
|
|
# board-specific options below
|
|
source "board/coreboot/Kconfig"
|
|
source "board/efi/Kconfig"
|
|
source "board/emulation/Kconfig"
|
|
source "board/google/Kconfig"
|
|
source "board/intel/Kconfig"
|
|
|
|
# platform-specific options below
|
|
source "arch/x86/cpu/baytrail/Kconfig"
|
|
source "arch/x86/cpu/coreboot/Kconfig"
|
|
source "arch/x86/cpu/ivybridge/Kconfig"
|
|
source "arch/x86/cpu/qemu/Kconfig"
|
|
source "arch/x86/cpu/quark/Kconfig"
|
|
source "arch/x86/cpu/queensbay/Kconfig"
|
|
|
|
# architecture-specific options below
|
|
|
|
config SYS_MALLOC_F_LEN
|
|
default 0x800
|
|
|
|
config RAMBASE
|
|
hex
|
|
default 0x100000
|
|
|
|
config XIP_ROM_SIZE
|
|
hex
|
|
depends on X86_RESET_VECTOR
|
|
default ROM_SIZE
|
|
|
|
config CPU_ADDR_BITS
|
|
int
|
|
default 36
|
|
|
|
config HPET_ADDRESS
|
|
hex
|
|
default 0xfed00000 if !HPET_ADDRESS_OVERRIDE
|
|
|
|
config SMM_TSEG
|
|
bool
|
|
default n
|
|
|
|
config SMM_TSEG_SIZE
|
|
hex
|
|
|
|
config X86_RESET_VECTOR
|
|
bool
|
|
default n
|
|
|
|
config RESET_SEG_START
|
|
hex
|
|
depends on X86_RESET_VECTOR
|
|
default 0xffff0000
|
|
|
|
config RESET_SEG_SIZE
|
|
hex
|
|
depends on X86_RESET_VECTOR
|
|
default 0x10000
|
|
|
|
config RESET_VEC_LOC
|
|
hex
|
|
depends on X86_RESET_VECTOR
|
|
default 0xfffffff0
|
|
|
|
config SYS_X86_START16
|
|
hex
|
|
depends on X86_RESET_VECTOR
|
|
default 0xfffff800
|
|
|
|
config BOARD_ROMSIZE_KB_512
|
|
bool
|
|
config BOARD_ROMSIZE_KB_1024
|
|
bool
|
|
config BOARD_ROMSIZE_KB_2048
|
|
bool
|
|
config BOARD_ROMSIZE_KB_4096
|
|
bool
|
|
config BOARD_ROMSIZE_KB_8192
|
|
bool
|
|
config BOARD_ROMSIZE_KB_16384
|
|
bool
|
|
|
|
choice
|
|
prompt "ROM chip size"
|
|
depends on X86_RESET_VECTOR
|
|
default UBOOT_ROMSIZE_KB_512 if BOARD_ROMSIZE_KB_512
|
|
default UBOOT_ROMSIZE_KB_1024 if BOARD_ROMSIZE_KB_1024
|
|
default UBOOT_ROMSIZE_KB_2048 if BOARD_ROMSIZE_KB_2048
|
|
default UBOOT_ROMSIZE_KB_4096 if BOARD_ROMSIZE_KB_4096
|
|
default UBOOT_ROMSIZE_KB_8192 if BOARD_ROMSIZE_KB_8192
|
|
default UBOOT_ROMSIZE_KB_16384 if BOARD_ROMSIZE_KB_16384
|
|
help
|
|
Select the size of the ROM chip you intend to flash U-Boot on.
|
|
|
|
The build system will take care of creating a u-boot.rom file
|
|
of the matching size.
|
|
|
|
config UBOOT_ROMSIZE_KB_512
|
|
bool "512 KB"
|
|
help
|
|
Choose this option if you have a 512 KB ROM chip.
|
|
|
|
config UBOOT_ROMSIZE_KB_1024
|
|
bool "1024 KB (1 MB)"
|
|
help
|
|
Choose this option if you have a 1024 KB (1 MB) ROM chip.
|
|
|
|
config UBOOT_ROMSIZE_KB_2048
|
|
bool "2048 KB (2 MB)"
|
|
help
|
|
Choose this option if you have a 2048 KB (2 MB) ROM chip.
|
|
|
|
config UBOOT_ROMSIZE_KB_4096
|
|
bool "4096 KB (4 MB)"
|
|
help
|
|
Choose this option if you have a 4096 KB (4 MB) ROM chip.
|
|
|
|
config UBOOT_ROMSIZE_KB_8192
|
|
bool "8192 KB (8 MB)"
|
|
help
|
|
Choose this option if you have a 8192 KB (8 MB) ROM chip.
|
|
|
|
config UBOOT_ROMSIZE_KB_16384
|
|
bool "16384 KB (16 MB)"
|
|
help
|
|
Choose this option if you have a 16384 KB (16 MB) ROM chip.
|
|
|
|
endchoice
|
|
|
|
# Map the config names to an integer (KB).
|
|
config UBOOT_ROMSIZE_KB
|
|
int
|
|
default 512 if UBOOT_ROMSIZE_KB_512
|
|
default 1024 if UBOOT_ROMSIZE_KB_1024
|
|
default 2048 if UBOOT_ROMSIZE_KB_2048
|
|
default 4096 if UBOOT_ROMSIZE_KB_4096
|
|
default 8192 if UBOOT_ROMSIZE_KB_8192
|
|
default 16384 if UBOOT_ROMSIZE_KB_16384
|
|
|
|
# Map the config names to a hex value (bytes).
|
|
config ROM_SIZE
|
|
hex
|
|
default 0x80000 if UBOOT_ROMSIZE_KB_512
|
|
default 0x100000 if UBOOT_ROMSIZE_KB_1024
|
|
default 0x200000 if UBOOT_ROMSIZE_KB_2048
|
|
default 0x400000 if UBOOT_ROMSIZE_KB_4096
|
|
default 0x800000 if UBOOT_ROMSIZE_KB_8192
|
|
default 0xc00000 if UBOOT_ROMSIZE_KB_12288
|
|
default 0x1000000 if UBOOT_ROMSIZE_KB_16384
|
|
|
|
config HAVE_INTEL_ME
|
|
bool "Platform requires Intel Management Engine"
|
|
help
|
|
Newer higher-end devices have an Intel Management Engine (ME)
|
|
which is a very large binary blob (typically 1.5MB) which is
|
|
required for the platform to work. This enforces a particular
|
|
SPI flash format. You will need to supply the me.bin file in
|
|
your board directory.
|
|
|
|
config X86_RAMTEST
|
|
bool "Perform a simple RAM test after SDRAM initialisation"
|
|
help
|
|
If there is something wrong with SDRAM then the platform will
|
|
often crash within U-Boot or the kernel. This option enables a
|
|
very simple RAM test that quickly checks whether the SDRAM seems
|
|
to work correctly. It is not exhaustive but can save time by
|
|
detecting obvious failures.
|
|
|
|
config HAVE_FSP
|
|
bool "Add an Firmware Support Package binary"
|
|
depends on !EFI
|
|
help
|
|
Select this option to add an Firmware Support Package binary to
|
|
the resulting U-Boot image. It is a binary blob which U-Boot uses
|
|
to set up SDRAM and other chipset specific initialization.
|
|
|
|
Note: Without this binary U-Boot will not be able to set up its
|
|
SDRAM so will not boot.
|
|
|
|
config FSP_FILE
|
|
string "Firmware Support Package binary filename"
|
|
depends on HAVE_FSP
|
|
default "fsp.bin"
|
|
help
|
|
The filename of the file to use as Firmware Support Package binary
|
|
in the board directory.
|
|
|
|
config FSP_ADDR
|
|
hex "Firmware Support Package binary location"
|
|
depends on HAVE_FSP
|
|
default 0xfffc0000
|
|
help
|
|
FSP is not Position Independent Code (PIC) and the whole FSP has to
|
|
be rebased if it is placed at a location which is different from the
|
|
perferred base address specified during the FSP build. Use Intel's
|
|
Binary Configuration Tool (BCT) to do the rebase.
|
|
|
|
The default base address of 0xfffc0000 indicates that the binary must
|
|
be located at offset 0xc0000 from the beginning of a 1MB flash device.
|
|
|
|
config FSP_TEMP_RAM_ADDR
|
|
hex
|
|
depends on HAVE_FSP
|
|
default 0x2000000
|
|
help
|
|
Stack top address which is used in fsp_init() after DRAM is ready and
|
|
CAR is disabled.
|
|
|
|
config FSP_SYS_MALLOC_F_LEN
|
|
hex
|
|
depends on HAVE_FSP
|
|
default 0x100000
|
|
help
|
|
Additional size of malloc() pool before relocation.
|
|
|
|
config FSP_USE_UPD
|
|
bool
|
|
depends on HAVE_FSP
|
|
default y
|
|
help
|
|
Most FSPs use UPD data region for some FSP customization. But there
|
|
are still some FSPs that might not even have UPD. For such FSPs,
|
|
override this to n in their platform Kconfig files.
|
|
|
|
config FSP_BROKEN_HOB
|
|
bool
|
|
depends on HAVE_FSP
|
|
help
|
|
Indicate some buggy FSPs that does not report memory used by FSP
|
|
itself as reserved in the resource descriptor HOB. Select this to
|
|
tell U-Boot to do some additional work to ensure U-Boot relocation
|
|
do not overwrite the important boot service data which is used by
|
|
FSP, otherwise the subsequent call to fsp_notify() will fail.
|
|
|
|
config ENABLE_MRC_CACHE
|
|
bool "Enable MRC cache"
|
|
depends on !EFI && !SYS_COREBOOT
|
|
help
|
|
Enable this feature to cause MRC data to be cached in NV storage
|
|
to be used for speeding up boot time on future reboots and/or
|
|
power cycles.
|
|
|
|
config SMP
|
|
bool "Enable Symmetric Multiprocessing"
|
|
default n
|
|
help
|
|
Enable use of more than one CPU in U-Boot and the Operating System
|
|
when loaded. Each CPU will be started up and information can be
|
|
obtained using the 'cpu' command. If this option is disabled, then
|
|
only one CPU will be enabled regardless of the number of CPUs
|
|
available.
|
|
|
|
config MAX_CPUS
|
|
int "Maximum number of CPUs permitted"
|
|
depends on SMP
|
|
default 4
|
|
help
|
|
When using multi-CPU chips it is possible for U-Boot to start up
|
|
more than one CPU. The stack memory used by all of these CPUs is
|
|
pre-allocated so at present U-Boot wants to know the maximum
|
|
number of CPUs that may be present. Set this to at least as high
|
|
as the number of CPUs in your system (it uses about 4KB of RAM for
|
|
each CPU).
|
|
|
|
config AP_STACK_SIZE
|
|
hex
|
|
depends on SMP
|
|
default 0x1000
|
|
help
|
|
Each additional CPU started by U-Boot requires its own stack. This
|
|
option sets the stack size used by each CPU and directly affects
|
|
the memory used by this initialisation process. Typically 4KB is
|
|
enough space.
|
|
|
|
config HAVE_VGA_BIOS
|
|
bool "Add a VGA BIOS image"
|
|
help
|
|
Select this option if you have a VGA BIOS image that you would
|
|
like to add to your ROM.
|
|
|
|
config VGA_BIOS_FILE
|
|
string "VGA BIOS image filename"
|
|
depends on HAVE_VGA_BIOS
|
|
default "vga.bin"
|
|
help
|
|
The filename of the VGA BIOS image in the board directory.
|
|
|
|
config VGA_BIOS_ADDR
|
|
hex "VGA BIOS image location"
|
|
depends on HAVE_VGA_BIOS
|
|
default 0xfff90000
|
|
help
|
|
The location of VGA BIOS image in the SPI flash. For example, base
|
|
address of 0xfff90000 indicates that the image will be put at offset
|
|
0x90000 from the beginning of a 1MB flash device.
|
|
|
|
menu "System tables"
|
|
depends on !EFI && !SYS_COREBOOT
|
|
|
|
config GENERATE_PIRQ_TABLE
|
|
bool "Generate a PIRQ table"
|
|
default n
|
|
help
|
|
Generate a PIRQ routing table for this board. The PIRQ routing table
|
|
is generated by U-Boot in the system memory from 0xf0000 to 0xfffff
|
|
at every 16-byte boundary with a PCI IRQ routing signature ("$PIR").
|
|
It specifies the interrupt router information as well how all the PCI
|
|
devices' interrupt pins are wired to PIRQs.
|
|
|
|
config GENERATE_SFI_TABLE
|
|
bool "Generate a SFI (Simple Firmware Interface) table"
|
|
help
|
|
The Simple Firmware Interface (SFI) provides a lightweight method
|
|
for platform firmware to pass information to the operating system
|
|
via static tables in memory. Kernel SFI support is required to
|
|
boot on SFI-only platforms. If you have ACPI tables then these are
|
|
used instead.
|
|
|
|
U-Boot writes this table in write_sfi_table() just before booting
|
|
the OS.
|
|
|
|
For more information, see http://simplefirmware.org
|
|
|
|
config GENERATE_MP_TABLE
|
|
bool "Generate an MP (Multi-Processor) table"
|
|
default n
|
|
help
|
|
Generate an MP (Multi-Processor) table for this board. The MP table
|
|
provides a way for the operating system to support for symmetric
|
|
multiprocessing as well as symmetric I/O interrupt handling with
|
|
the local APIC and I/O APIC.
|
|
|
|
config GENERATE_ACPI_TABLE
|
|
bool "Generate an ACPI (Advanced Configuration and Power Interface) table"
|
|
default n
|
|
help
|
|
The Advanced Configuration and Power Interface (ACPI) specification
|
|
provides an open standard for device configuration and management
|
|
by the operating system. It defines platform-independent interfaces
|
|
for configuration and power management monitoring.
|
|
|
|
config QEMU_ACPI_TABLE
|
|
bool "Load ACPI table from QEMU fw_cfg interface"
|
|
depends on GENERATE_ACPI_TABLE && QEMU
|
|
default y
|
|
help
|
|
By default, U-Boot generates its own ACPI tables. This option, if
|
|
enabled, disables U-Boot's version and loads ACPI tables generated
|
|
by QEMU.
|
|
|
|
config GENERATE_SMBIOS_TABLE
|
|
bool "Generate an SMBIOS (System Management BIOS) table"
|
|
default y
|
|
help
|
|
The System Management BIOS (SMBIOS) specification addresses how
|
|
motherboard and system vendors present management information about
|
|
their products in a standard format by extending the BIOS interface
|
|
on Intel architecture systems.
|
|
|
|
Check http://www.dmtf.org/standards/smbios for details.
|
|
|
|
endmenu
|
|
|
|
config MAX_PIRQ_LINKS
|
|
int
|
|
default 8
|
|
help
|
|
This variable specifies the number of PIRQ interrupt links which are
|
|
routable. On most older chipsets, this is 4, PIRQA through PIRQD.
|
|
Some newer chipsets offer more than four links, commonly up to PIRQH.
|
|
|
|
config IRQ_SLOT_COUNT
|
|
int
|
|
default 128
|
|
help
|
|
U-Boot can support up to 254 IRQ slot info in the PIRQ routing table
|
|
which in turns forms a table of exact 4KiB. The default value 128
|
|
should be enough for most boards. If this does not fit your board,
|
|
change it according to your needs.
|
|
|
|
config PCIE_ECAM_BASE
|
|
hex
|
|
default 0xe0000000
|
|
help
|
|
This is the memory-mapped address of PCI configuration space, which
|
|
is only available through the Enhanced Configuration Access
|
|
Mechanism (ECAM) with PCI Express. It can be set up almost
|
|
anywhere. Before it is set up, it is possible to access PCI
|
|
configuration space through I/O access, but memory access is more
|
|
convenient. Using this, PCI can be scanned and configured. This
|
|
should be set to a region that does not conflict with memory
|
|
assigned to PCI devices - i.e. the memory and prefetch regions, as
|
|
passed to pci_set_region().
|
|
|
|
config PCIE_ECAM_SIZE
|
|
hex
|
|
default 0x10000000
|
|
help
|
|
This is the size of memory-mapped address of PCI configuration space,
|
|
which is only available through the Enhanced Configuration Access
|
|
Mechanism (ECAM) with PCI Express. Each bus consumes 1 MiB memory,
|
|
so a default 0x10000000 size covers all of the 256 buses which is the
|
|
maximum number of PCI buses as defined by the PCI specification.
|
|
|
|
config I8259_PIC
|
|
bool
|
|
default y
|
|
help
|
|
Intel 8259 ISA compatible chipset incorporates two 8259 (master and
|
|
slave) interrupt controllers. Include this to have U-Boot set up
|
|
the interrupt correctly.
|
|
|
|
config I8254_TIMER
|
|
bool
|
|
default y
|
|
help
|
|
Intel 8254 timer contains three counters which have fixed uses.
|
|
Include this to have U-Boot set up the timer correctly.
|
|
|
|
config I8042_KEYB
|
|
default y
|
|
|
|
config DM_KEYBOARD
|
|
default y
|
|
|
|
source "arch/x86/lib/efi/Kconfig"
|
|
|
|
endmenu
|