mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-17 18:28:55 +00:00
b215614638
Add quirk to disable high speed incase the high speed was broken.This solves the issue where the the controller is used in High Speed Mode and the the hold time requirement for the JEDEC/MMC 4.41 specification is NOT met. This timing issue is not on all boards and hence provided config option to enable it when required. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Emil Lenchak <emill@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
64 lines
1.4 KiB
C
64 lines
1.4 KiB
C
/*
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* (C) Copyright 2013 - 2015 Xilinx, Inc.
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*
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* Xilinx Zynq SD Host Controller Interface
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <dm.h>
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#include <fdtdec.h>
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#include <libfdt.h>
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#include <malloc.h>
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#include <sdhci.h>
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#ifndef CONFIG_ZYNQ_SDHCI_MIN_FREQ
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# define CONFIG_ZYNQ_SDHCI_MIN_FREQ 0
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#endif
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static int arasan_sdhci_probe(struct udevice *dev)
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{
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struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
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struct sdhci_host *host = dev_get_priv(dev);
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host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD |
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SDHCI_QUIRK_BROKEN_R1B;
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#ifdef CONFIG_ZYNQ_HISPD_BROKEN
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host->quirks |= SDHCI_QUIRK_NO_HISPD_BIT;
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#endif
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host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
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add_sdhci(host, CONFIG_ZYNQ_SDHCI_MAX_FREQ,
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CONFIG_ZYNQ_SDHCI_MIN_FREQ);
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upriv->mmc = host->mmc;
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return 0;
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}
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static int arasan_sdhci_ofdata_to_platdata(struct udevice *dev)
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{
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struct sdhci_host *host = dev_get_priv(dev);
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host->name = (char *)dev->name;
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host->ioaddr = (void *)dev_get_addr(dev);
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return 0;
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}
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static const struct udevice_id arasan_sdhci_ids[] = {
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{ .compatible = "arasan,sdhci-8.9a" },
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{ }
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};
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U_BOOT_DRIVER(arasan_sdhci_drv) = {
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.name = "arasan_sdhci",
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.id = UCLASS_MMC,
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.of_match = arasan_sdhci_ids,
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.ofdata_to_platdata = arasan_sdhci_ofdata_to_platdata,
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.probe = arasan_sdhci_probe,
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.priv_auto_alloc_size = sizeof(struct sdhci_host),
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};
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