mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-16 17:58:23 +00:00
47c5705d82
This change allows to reserve enough space at the end of board SDRAM to store two copies of U-Boot and malloc heap. Due to selection of the CONFIG_SYS_TEXT_BASE the second code/data copying is not avoided, first of all this may depend on a used toolchain, secondly at this point some level of volatility is wanted to do more platform changes and do not care about probably changed calculated in runtime relocation offset. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
106 lines
3.1 KiB
C
106 lines
3.1 KiB
C
#ifndef __CONFIG_H
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#define __CONFIG_H
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#define CONFIG_CPU_SH7751 1
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#define CONFIG_CPU_SH_TYPE_R 1
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#define CONFIG_R2DPLUS 1
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#define __LITTLE_ENDIAN__ 1
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#define CONFIG_DISPLAY_BOARDINFO
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/*
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* Command line configuration.
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*/
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#define CONFIG_CMD_PCI
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#define CONFIG_CMD_IDE
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#define CONFIG_DOS_PARTITION
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#define CONFIG_CMD_SH_ZIMAGEBOOT
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/* SCIF */
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#define CONFIG_SCIF_CONSOLE 1
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#define CONFIG_BAUDRATE 115200
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#define CONFIG_CONS_SCIF1 1
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#define CONFIG_BOARD_LATE_INIT
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#define CONFIG_BOOTARGS "console=ttySC0,115200"
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#define CONFIG_ENV_OVERWRITE 1
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/* SDRAM */
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#define CONFIG_SYS_SDRAM_BASE 0x8C000000
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#define CONFIG_SYS_SDRAM_SIZE 0x04000000
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#define CONFIG_SYS_TEXT_BASE 0x8FE00000
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#define CONFIG_SYS_LONGHELP
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#define CONFIG_SYS_CBSIZE 256
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#define CONFIG_SYS_PBSIZE 256
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#define CONFIG_SYS_MAXARGS 16
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#define CONFIG_SYS_BARGSIZE 512
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#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE)
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#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE - 0x100000)
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#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 32 * 1024 * 1024)
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/* Address of u-boot image in Flash */
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#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE)
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#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
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/* Size of DRAM reserved for malloc() use */
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#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
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#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
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/*
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* NOR Flash ( Spantion S29GL256P )
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*/
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#define CONFIG_SYS_FLASH_CFI
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#define CONFIG_FLASH_CFI_DRIVER
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#define CONFIG_SYS_FLASH_BASE (0xA0000000)
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#define CONFIG_SYS_MAX_FLASH_BANKS (1)
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#define CONFIG_SYS_MAX_FLASH_SECT 256
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#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
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#define CONFIG_ENV_IS_IN_FLASH
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#define CONFIG_ENV_SECT_SIZE 0x40000
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#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
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#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
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/*
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* SuperH Clock setting
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*/
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#define CONFIG_SYS_CLK_FREQ 60000000
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#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
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#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
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#define CONFIG_SYS_TMU_CLK_DIV 4
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#define CONFIG_SYS_PLL_SETTLING_TIME 100/* in us */
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/*
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* IDE support
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*/
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#define CONFIG_IDE_RESET 1
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#define CONFIG_SYS_PIO_MODE 1
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#define CONFIG_SYS_IDE_MAXBUS 1 /* IDE bus */
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#define CONFIG_SYS_IDE_MAXDEVICE 1
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#define CONFIG_SYS_ATA_BASE_ADDR 0xb4000000
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#define CONFIG_SYS_ATA_STRIDE 2 /* 1bit shift */
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#define CONFIG_SYS_ATA_DATA_OFFSET 0x1000 /* data reg offset */
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#define CONFIG_SYS_ATA_REG_OFFSET 0x1000 /* reg offset */
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#define CONFIG_SYS_ATA_ALT_OFFSET 0x800 /* alternate register offset */
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#define CONFIG_IDE_SWAP_IO
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/*
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* SuperH PCI Bridge Configration
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*/
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#define CONFIG_SH4_PCI
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#define CONFIG_SH7751_PCI
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#define CONFIG_PCI_SCAN_SHOW 1
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#define __mem_pci
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#define CONFIG_PCI_MEM_BUS 0xFD000000 /* Memory space base addr */
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#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
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#define CONFIG_PCI_MEM_SIZE 0x01000000 /* Size of Memory window */
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#define CONFIG_PCI_IO_BUS 0xFE240000 /* IO space base address */
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#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
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#define CONFIG_PCI_IO_SIZE 0x00040000 /* Size of IO window */
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#define CONFIG_PCI_SYS_BUS CONFIG_SYS_SDRAM_BASE
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#define CONFIG_PCI_SYS_PHYS CONFIG_SYS_SDRAM_BASE
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#define CONFIG_PCI_SYS_SIZE CONFIG_SYS_SDRAM_SIZE
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#endif /* __CONFIG_H */
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