mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-16 17:58:23 +00:00
904110c7ac
Up to now, there are 3 kind of SoCs under Layerscape Chassis 2, like LS1043A, LS1046A and LS1012A. But the clocks tree has a lot of differences, for instance, the IP modules have different dividers to derive its clock from Platform PLL. And the core cluster PLL and platform PLL maybe have different reference clocks, such as LS1012A. Another problem is which clock/PLL should be described by sys_info->freq_systembus, it is confused in Layerscape Chissis 2. This patch is to bind the sys_info->freq_systembus to the Platform PLL, and handle the different divider of IP modules separately between different SoCs, and separate reference clocks of core cluster PLL and platform PLL. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
131 lines
3.5 KiB
C
131 lines
3.5 KiB
C
/*
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* Copyright 2016 Freescale Semiconductor
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __LS1012A_COMMON_H
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#define __LS1012A_COMMON_H
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#define CONFIG_FSL_LAYERSCAPE
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#define CONFIG_GICV2
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#include <asm/arch/config.h>
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#define CONFIG_SYS_NO_FLASH
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#define CONFIG_SUPPORT_RAW_INITRD
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#define CONFIG_DISPLAY_BOARDINFO_LATE
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#define CONFIG_SYS_TEXT_BASE 0x40100000
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#define CONFIG_SYS_CLK_FREQ 125000000
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#define CONFIG_SKIP_LOWLEVEL_INIT
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#define CONFIG_BOARD_EARLY_INIT_F 1
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#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
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#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
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#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
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#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
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#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
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/* Generic Timer Definitions */
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#define COUNTER_FREQUENCY CONFIG_SYS_CLK_FREQ/4 /* 25MHz */
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/* CSU */
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#define CONFIG_LAYERSCAPE_NS_ACCESS
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/* Size of malloc() pool */
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#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024)
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/*SPI device */
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#ifdef CONFIG_QSPI_BOOT
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#define CONFIG_SYS_QE_FW_IN_SPIFLASH
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#define CONFIG_SYS_FMAN_FW_ADDR 0x400d0000
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#define CONFIG_ENV_SPI_BUS 0
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#define CONFIG_ENV_SPI_CS 0
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#define CONFIG_ENV_SPI_MAX_HZ 1000000
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#define CONFIG_ENV_SPI_MODE 0x03
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#define CONFIG_SPI_FLASH_SPANSION
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#define CONFIG_FSL_SPI_INTERFACE
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#define CONFIG_SF_DATAFLASH
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#define CONFIG_FSL_QSPI
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#define QSPI0_AMBA_BASE 0x40000000
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#define CONFIG_SPI_FLASH_SPANSION
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#define CONFIG_SPI_FLASH_BAR
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#define FSL_QSPI_FLASH_SIZE (1 << 24)
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#define FSL_QSPI_FLASH_NUM 2
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/*
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* Environment
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*/
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_ENV_IS_IN_SPI_FLASH
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#define CONFIG_ENV_SIZE 0x40000 /* 256KB */
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#define CONFIG_ENV_OFFSET 0x200000 /* 2MB */
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#define CONFIG_ENV_SECT_SIZE 0x40000
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#endif
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/* I2C */
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#define CONFIG_SYS_I2C
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#define CONFIG_SYS_I2C_MXC
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#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
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#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
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#define CONFIG_CONS_INDEX 1
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#define CONFIG_SYS_NS16550_SERIAL
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#define CONFIG_SYS_NS16550_REG_SIZE 1
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#define CONFIG_SYS_NS16550_CLK (get_serial_clock())
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#define CONFIG_BAUDRATE 115200
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#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
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/* Command line configuration */
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#define CONFIG_CMD_ENV
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#undef CONFIG_CMD_IMLS
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#define CONFIG_ARCH_EARLY_INIT_R
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#define CONFIG_SYS_HZ 1000
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#define CONFIG_HWCONFIG
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#define HWCONFIG_BUFFER_SIZE 128
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/* Initial environment variables */
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"verify=no\0" \
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"loadaddr=0x80100000\0" \
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"kernel_addr=0x100000\0" \
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"fdt_high=0xffffffffffffffff\0" \
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"initrd_high=0xffffffffffffffff\0" \
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"kernel_start=0xa00000\0" \
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"kernel_load=0xa0000000\0" \
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"kernel_size=0x2800000\0" \
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#define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/ram0 " \
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"earlycon=uart8250,mmio,0x21c0500 quiet lpj=250000"
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#define CONFIG_BOOTCOMMAND "sf probe 0:0; sf read $kernel_load "\
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"$kernel_start $kernel_size && "\
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"bootm $kernel_load"
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/* Monitor Command Prompt */
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#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
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sizeof(CONFIG_SYS_PROMPT) + 16)
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */
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#define CONFIG_SYS_LONGHELP
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#define CONFIG_CMDLINE_EDITING 1
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#define CONFIG_AUTO_COMPLETE
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#define CONFIG_SYS_MAXARGS 64 /* max command args */
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#define CONFIG_PANIC_HANG
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#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
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#include <asm/fsl_secure_boot.h>
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#endif /* __LS1012A_COMMON_H */
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