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https://github.com/AsahiLinux/u-boot
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1037c5ba37
In StarFive VF2 board. pcie0 connect to VTI usb controller. Enable it to support usb host. Signed-off-by: Minda Chen <minda.chen@starfivetech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
370 lines
6.9 KiB
Text
370 lines
6.9 KiB
Text
// SPDX-License-Identifier: GPL-2.0 OR MIT
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/*
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* Copyright (C) 2022 StarFive Technology Co., Ltd.
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*/
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/dts-v1/;
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#include "jh7110.dtsi"
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#include <dt-bindings/pinctrl/pinctrl-starfive-jh7110.h>
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#include <dt-bindings/gpio/gpio.h>
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/ {
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aliases {
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serial0 = &uart0;
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spi0 = &qspi;
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mmc0 = &mmc0;
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mmc1 = &mmc1;
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i2c0 = &i2c0;
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i2c2 = &i2c2;
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i2c5 = &i2c5;
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i2c6 = &i2c6;
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ethernet0 = &gmac0;
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ethernet1 = &gmac1;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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cpus {
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timebase-frequency = <4000000>;
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};
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memory@40000000 {
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device_type = "memory";
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reg = <0x0 0x40000000 0x2 0x0>;
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};
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};
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&osc {
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clock-frequency = <24000000>;
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};
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&rtc_osc {
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clock-frequency = <32768>;
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};
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&gmac0_rmii_refin {
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clock-frequency = <50000000>;
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};
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&gmac0_rgmii_rxin {
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clock-frequency = <125000000>;
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};
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&gmac1_rmii_refin {
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clock-frequency = <50000000>;
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};
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&gmac1_rgmii_rxin {
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clock-frequency = <125000000>;
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};
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&i2stx_bclk_ext {
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clock-frequency = <12288000>;
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};
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&i2stx_lrck_ext {
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clock-frequency = <192000>;
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};
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&i2srx_bclk_ext {
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clock-frequency = <12288000>;
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};
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&i2srx_lrck_ext {
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clock-frequency = <192000>;
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};
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&tdm_ext {
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clock-frequency = <49152000>;
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};
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&mclk_ext {
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clock-frequency = <12288000>;
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};
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&uart0 {
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reg-offset = <0>;
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current-speed = <115200>;
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clock-frequency = <24000000>;
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pinctrl-names = "default";
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pinctrl-0 = <&uart0_pins>;
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status = "okay";
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};
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&i2c0 {
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clock-frequency = <100000>;
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i2c-sda-hold-time-ns = <300>;
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i2c-sda-falling-time-ns = <510>;
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i2c-scl-falling-time-ns = <510>;
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pinctrl-names = "default";
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pinctrl-0 = <&i2c0_pins>;
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status = "okay";
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};
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&i2c2 {
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clock-frequency = <100000>;
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i2c-sda-hold-time-ns = <300>;
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i2c-sda-falling-time-ns = <510>;
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i2c-scl-falling-time-ns = <510>;
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pinctrl-names = "default";
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pinctrl-0 = <&i2c2_pins>;
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status = "okay";
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};
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&i2c5 {
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clock-frequency = <100000>;
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i2c-sda-hold-time-ns = <300>;
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i2c-sda-falling-time-ns = <510>;
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i2c-scl-falling-time-ns = <510>;
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pinctrl-names = "default";
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pinctrl-0 = <&i2c5_pins>;
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status = "okay";
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eeprom@50 {
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compatible = "atmel,24c04";
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reg = <0x50>;
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pagesize = <16>;
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};
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};
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&i2c6 {
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clock-frequency = <100000>;
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i2c-sda-hold-time-ns = <300>;
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i2c-sda-falling-time-ns = <510>;
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i2c-scl-falling-time-ns = <510>;
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pinctrl-names = "default";
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pinctrl-0 = <&i2c6_pins>;
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status = "okay";
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};
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&sysgpio {
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status = "okay";
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uart0_pins: uart0-0 {
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tx-pins {
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pinmux = <GPIOMUX(5, GPOUT_SYS_UART0_TX,
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GPOEN_ENABLE,
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GPI_NONE)>;
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bias-disable;
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drive-strength = <12>;
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input-disable;
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input-schmitt-disable;
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slew-rate = <0>;
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};
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rx-pins {
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pinmux = <GPIOMUX(6, GPOUT_LOW,
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GPOEN_DISABLE,
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GPI_SYS_UART0_RX)>;
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bias-disable; /* external pull-up */
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drive-strength = <2>;
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input-enable;
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input-schmitt-enable;
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slew-rate = <0>;
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};
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};
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i2c0_pins: i2c0-0 {
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i2c-pins {
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pinmux = <GPIOMUX(57, GPOUT_LOW,
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GPOEN_SYS_I2C0_CLK,
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GPI_SYS_I2C0_CLK)>,
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<GPIOMUX(58, GPOUT_LOW,
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GPOEN_SYS_I2C0_DATA,
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GPI_SYS_I2C0_DATA)>;
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bias-disable; /* external pull-up */
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input-enable;
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input-schmitt-enable;
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};
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};
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i2c2_pins: i2c2-0 {
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i2c-pins {
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pinmux = <GPIOMUX(3, GPOUT_LOW,
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GPOEN_SYS_I2C2_CLK,
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GPI_SYS_I2C2_CLK)>,
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<GPIOMUX(2, GPOUT_LOW,
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GPOEN_SYS_I2C2_DATA,
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GPI_SYS_I2C2_DATA)>;
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bias-disable; /* external pull-up */
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input-enable;
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input-schmitt-enable;
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};
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};
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i2c5_pins: i2c5-0 {
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i2c-pins {
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pinmux = <GPIOMUX(19, GPOUT_LOW,
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GPOEN_SYS_I2C5_CLK,
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GPI_SYS_I2C5_CLK)>,
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<GPIOMUX(20, GPOUT_LOW,
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GPOEN_SYS_I2C5_DATA,
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GPI_SYS_I2C5_DATA)>;
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bias-disable; /* external pull-up */
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input-enable;
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input-schmitt-enable;
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};
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};
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i2c6_pins: i2c6-0 {
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i2c-pins {
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pinmux = <GPIOMUX(16, GPOUT_LOW,
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GPOEN_SYS_I2C6_CLK,
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GPI_SYS_I2C6_CLK)>,
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<GPIOMUX(17, GPOUT_LOW,
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GPOEN_SYS_I2C6_DATA,
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GPI_SYS_I2C6_DATA)>;
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bias-disable; /* external pull-up */
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input-enable;
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input-schmitt-enable;
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};
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};
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mmc0_pins: mmc0-pins {
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mmc0-pins-rest {
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pinmux = <GPIOMUX(62, GPOUT_SYS_SDIO0_RST,
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GPOEN_ENABLE, GPI_NONE)>;
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bias-pull-up;
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drive-strength = <12>;
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input-disable;
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input-schmitt-disable;
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slew-rate = <0>;
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};
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};
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mmc1_pins: mmc1-pins {
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mmc1-pins0 {
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pinmux = <GPIOMUX(10, GPOUT_SYS_SDIO1_CLK,
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GPOEN_ENABLE, GPI_NONE)>;
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bias-pull-up;
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drive-strength = <12>;
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input-disable;
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input-schmitt-disable;
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slew-rate = <0>;
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};
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mmc1-pins1 {
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pinmux = <GPIOMUX(9, GPOUT_SYS_SDIO1_CMD,
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GPOEN_SYS_SDIO1_CMD, GPI_SYS_SDIO1_CMD)>,
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<GPIOMUX(11, GPOUT_SYS_SDIO1_DATA0,
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GPOEN_SYS_SDIO1_DATA0, GPI_SYS_SDIO1_DATA0)>,
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<GPIOMUX(12, GPOUT_SYS_SDIO1_DATA1,
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GPOEN_SYS_SDIO1_DATA1, GPI_SYS_SDIO1_DATA1)>,
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<GPIOMUX(7, GPOUT_SYS_SDIO1_DATA2,
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GPOEN_SYS_SDIO1_DATA2, GPI_SYS_SDIO1_DATA2)>,
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<GPIOMUX(8, GPOUT_SYS_SDIO1_DATA3,
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GPOEN_SYS_SDIO1_DATA3, GPI_SYS_SDIO1_DATA3)>;
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bias-pull-up;
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drive-strength = <12>;
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input-enable;
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input-schmitt-enable;
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slew-rate = <0>;
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};
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};
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};
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&mmc0 {
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compatible = "snps,dw-mshc";
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max-frequency = <100000000>;
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bus-width = <8>;
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pinctrl-names = "default";
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pinctrl-0 = <&mmc0_pins>;
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cap-mmc-highspeed;
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mmc-ddr-1_8v;
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mmc-hs200-1_8v;
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non-removable;
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cap-mmc-hw-reset;
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post-power-on-delay-ms = <200>;
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status = "okay";
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};
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&mmc1 {
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compatible = "snps,dw-mshc";
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max-frequency = <100000000>;
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bus-width = <4>;
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pinctrl-names = "default";
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pinctrl-0 = <&mmc1_pins>;
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no-sdio;
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no-mmc;
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broken-cd;
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cap-sd-highspeed;
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post-power-on-delay-ms = <200>;
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status = "okay";
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};
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&qspi {
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spi-max-frequency = <250000000>;
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status = "okay";
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nor-flash@0 {
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compatible = "jedec,spi-nor";
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reg=<0>;
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spi-max-frequency = <100000000>;
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cdns,tshsl-ns = <1>;
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cdns,tsd2d-ns = <1>;
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cdns,tchsh-ns = <1>;
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cdns,tslch-ns = <1>;
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};
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};
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&pcie0 {
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reset-gpios = <&sysgpio 26 GPIO_ACTIVE_LOW>;
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status = "okay";
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};
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&pcie1 {
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reset-gpios = <&sysgpio 28 GPIO_ACTIVE_LOW>;
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status = "okay";
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};
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&syscrg {
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assigned-clocks = <&syscrg JH7110_SYSCLK_CPU_ROOT>,
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<&syscrg JH7110_SYSCLK_BUS_ROOT>,
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<&syscrg JH7110_SYSCLK_PERH_ROOT>,
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<&syscrg JH7110_SYSCLK_QSPI_REF>;
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assigned-clock-parents = <&pllclk JH7110_SYSCLK_PLL0_OUT>,
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<&pllclk JH7110_SYSCLK_PLL2_OUT>,
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<&pllclk JH7110_SYSCLK_PLL2_OUT>,
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<&syscrg JH7110_SYSCLK_QSPI_REF_SRC>;
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assigned-clock-rates = <0>, <0>, <0>, <0>;
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};
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&aoncrg {
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assigned-clocks = <&aoncrg JH7110_AONCLK_APB_FUNC>;
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assigned-clock-parents = <&osc>;
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assigned-clock-rates = <0>;
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};
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&gmac0 {
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phy-handle = <&phy0>;
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phy-mode = "rgmii-id";
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status = "okay";
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "snps,dwmac-mdio";
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phy0: ethernet-phy@0 {
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reg = <0>;
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};
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};
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};
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&gmac1 {
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phy-handle = <&phy1>;
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phy-mode = "rgmii-id";
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status = "okay";
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "snps,dwmac-mdio";
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phy1: ethernet-phy@1 {
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reg = <0>;
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};
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};
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};
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