mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-18 10:48:51 +00:00
4e8b7544b7
Rename mc13783-rtc so that it can be used for both MC13783 and MC13892 PMICs. efikamx board, for example, does use a MC13892 PMIC, but the RTC selection is currently made as: #define CONFIG_RTC_MC13783 ,which is not very obvious. Let the MC13783 and MC13892 RTC be selected by: #define CONFIG_RTC_MC13XXX Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de>
316 lines
9.6 KiB
C
316 lines
9.6 KiB
C
/*
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* Copyright (C) 2009, Ilya Yanok, Emcraft Systems, <yanok@emcraft.com>
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*
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* Configuration settings for the Dave/DENX QongEVB-LITE board.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#include <asm/arch/imx-regs.h>
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/* High Level Configuration Options */
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#define CONFIG_ARM1136 /* This is an arm1136 CPU core */
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#define CONFIG_MX31 /* in a mx31 */
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#define CONFIG_QONG
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#define CONFIG_MX31_HCLK_FREQ 26000000 /* 26MHz */
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#define CONFIG_MX31_CLK32 32768
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#define CONFIG_DISPLAY_CPUINFO
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#define CONFIG_DISPLAY_BOARDINFO
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#define CONFIG_SYS_TEXT_BASE 0xa0000000
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#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
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#define CONFIG_SETUP_MEMORY_TAGS
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#define CONFIG_INITRD_TAG
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/*
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* Size of malloc() pool
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*/
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#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024)
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/*
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* Hardware drivers
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*/
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#define CONFIG_MXC_UART 1
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#define CONFIG_SYS_MX31_UART1 1
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#define CONFIG_MXC_GPIO
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#define CONFIG_HW_WATCHDOG
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#define CONFIG_MXC_SPI
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#define CONFIG_DEFAULT_SPI_BUS 1
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#define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_0 | SPI_CS_HIGH)
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#define CONFIG_RTC_MC13XXX
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#define CONFIG_PMIC
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#define CONFIG_PMIC_SPI
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#define CONFIG_PMIC_FSL
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#define CONFIG_FSL_PMIC_BUS 1
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#define CONFIG_FSL_PMIC_CS 0
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#define CONFIG_FSL_PMIC_CLK 100000
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#define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH)
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#define CONFIG_FSL_PMIC_BITLEN 32
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/* FPGA */
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#define CONFIG_FPGA
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#define CONFIG_QONG_FPGA
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#define CONFIG_FPGA_BASE (CS1_BASE)
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#define CONFIG_FPGA_LATTICE
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#define CONFIG_FPGA_COUNT 1
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#ifdef CONFIG_QONG_FPGA
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/* Ethernet */
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#define CONFIG_DNET
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#define CONFIG_DNET_BASE (CS1_BASE + QONG_FPGA_PERIPH_SIZE)
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/* Framebuffer and LCD */
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#define CONFIG_VIDEO
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#define CONFIG_CFB_CONSOLE
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#define CONFIG_VIDEO_MX3
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#define CONFIG_VIDEO_LOGO
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#define CONFIG_VIDEO_SW_CURSOR
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#define CONFIG_VGA_AS_SINGLE_DEVICE
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#define CONFIG_SYS_CONSOLE_IS_IN_ENV
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#define CONFIG_SPLASH_SCREEN
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#define CONFIG_CMD_BMP
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#define CONFIG_BMP_16BPP
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/* USB */
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#define CONFIG_CMD_USB
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#ifdef CONFIG_CMD_USB
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#define CONFIG_USB_EHCI /* Enable EHCI USB support */
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#define CONFIG_USB_EHCI_MXC
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#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
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#define CONFIG_MXC_USB_PORT 2
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#define CONFIG_MXC_USB_PORTSC (MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT)
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#define CONFIG_MXC_USB_FLAGS MXC_EHCI_POWER_PINS_ENABLED
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#define CONFIG_EHCI_IS_TDI
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#define CONFIG_USB_STORAGE
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#define CONFIG_DOS_PARTITION
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#define CONFIG_SUPPORT_VFAT
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#define CONFIG_CMD_EXT2
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#define CONFIG_CMD_FAT
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#endif /* CONFIG_CMD_USB */
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/*
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* Reducing the ARP timeout from default 5 seconds to 200ms we speed up the
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* initial TFTP transfer, should the user wish one, significantly.
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*/
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#define CONFIG_ARP_TIMEOUT 200UL
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#endif /* CONFIG_QONG_FPGA */
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#define CONFIG_CONS_INDEX 1
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#define CONFIG_BAUDRATE 115200
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#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200}
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/***********************************************************
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* Command definition
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***********************************************************/
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#include <config_cmd_default.h>
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#define CONFIG_CMD_CACHE
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#define CONFIG_CMD_DATE
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#define CONFIG_CMD_DHCP
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#define CONFIG_CMD_MII
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#define CONFIG_CMD_NAND
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#define CONFIG_CMD_NET
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#define CONFIG_CMD_PING
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#define CONFIG_CMD_SETEXPR
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#define CONFIG_CMD_SPI
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#define CONFIG_BOARD_LATE_INIT
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#define CONFIG_BOOTDELAY 5
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#define CONFIG_LOADADDR 0x80800000 /* loadaddr env var */
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#define xstr(s) str(s)
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#define str(s) #s
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"netdev=eth0\0" \
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"nfsargs=setenv bootargs root=/dev/nfs rw " \
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"nfsroot=${serverip}:${rootpath}\0" \
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"ramargs=setenv bootargs root=/dev/ram rw\0" \
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"addip=setenv bootargs ${bootargs} " \
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"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
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":${hostname}:${netdev}:off panic=1\0" \
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"addtty=setenv bootargs ${bootargs}" \
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" console=ttymxc0,${baudrate}\0" \
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"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
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"addmisc=setenv bootargs ${bootargs}\0" \
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"uboot_addr=A0000000\0" \
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"kernel_addr=A00C0000\0" \
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"ramdisk_addr=A0300000\0" \
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"u-boot=qong/u-boot.bin\0" \
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"kernel_addr_r=80800000\0" \
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"hostname=qong\0" \
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"bootfile=qong/uImage\0" \
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"rootpath=/opt/eldk-4.2-arm/armVFP\0" \
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"flash_self=run ramargs addip addtty addmtd addmisc;" \
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"bootm ${kernel_addr} ${ramdisk_addr}\0" \
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"flash_nfs=run nfsargs addip addtty addmtd addmisc;" \
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"bootm ${kernel_addr}\0" \
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"net_nfs=tftp ${kernel_addr_r} ${bootfile};" \
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"run nfsargs addip addtty addmtd addmisc;" \
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"bootm\0" \
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"bootcmd=run flash_self\0" \
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"load=tftp ${loadaddr} ${u-boot}\0" \
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"update=protect off " xstr(CONFIG_SYS_MONITOR_BASE) \
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" +${filesize};era " xstr(CONFIG_SYS_MONITOR_BASE) \
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" +${filesize};cp.b ${fileaddr} " \
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xstr(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \
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"upd=run load update\0" \
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"videomode=video=ctfb:x:640,y:480,depth:16,mode:0,pclk:40000," \
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"le:120,ri:40,up:35,lo:10,hs:30,vs:3,sync:100663296," \
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"vmode:0\0" \
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/*
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* Miscellaneous configurable options
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*/
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#define CONFIG_SYS_LONGHELP /* undef to save memory */
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#define CONFIG_SYS_PROMPT "=> "
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#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
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/* Print Buffer Size */
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
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sizeof(CONFIG_SYS_PROMPT) + 16)
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#define CONFIG_SYS_MAXARGS 32 /* max number of command args */
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/* Boot Argument Buffer Size */
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
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/* memtest works on first 255MB of RAM */
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#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1
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#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 0xff000000)
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#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
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#define CONFIG_SYS_HZ 1000
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#define CONFIG_CMDLINE_EDITING
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#define CONFIG_SYS_HUSH_PARSER /* Use the HUSH parser */
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#ifdef CONFIG_SYS_HUSH_PARSER
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#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
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#endif
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#define CONFIG_MISC_INIT_R
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/*-----------------------------------------------------------------------
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* Stack sizes
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*
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* The stack sizes are set up in start.S using the settings below
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*/
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#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
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/*-----------------------------------------------------------------------
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* Physical Memory Map
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*/
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#define CONFIG_NR_DRAM_BANKS 1
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#define PHYS_SDRAM_1 CSD0_BASE
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#define PHYS_SDRAM_1_SIZE 0x10000000 /* 256 MB */
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/*
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* NAND driver
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*/
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#ifndef __ASSEMBLY__
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extern void qong_nand_plat_init(void *chip);
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extern int qong_nand_rdy(void *chip);
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#endif
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#define CONFIG_NAND_PLAT
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define CONFIG_SYS_NAND_BASE CS3_BASE
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#define NAND_PLAT_INIT() qong_nand_plat_init(nand)
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#define QONG_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 24))
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#define QONG_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 23))
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#define QONG_NAND_WRITE(addr, cmd) \
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do { \
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__REG8(addr) = cmd; \
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} while (0)
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#define NAND_PLAT_WRITE_CMD(chip, cmd) QONG_NAND_WRITE(QONG_NAND_CLE(chip), cmd)
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#define NAND_PLAT_WRITE_ADR(chip, cmd) QONG_NAND_WRITE(QONG_NAND_ALE(chip), cmd)
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#define NAND_PLAT_DEV_READY(chip) (qong_nand_rdy(chip))
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/*-----------------------------------------------------------------------
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* FLASH and environment organization
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*/
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#define CONFIG_SYS_FLASH_BASE CS0_BASE
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#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
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/* max number of sectors on one chip */
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#define CONFIG_SYS_MAX_FLASH_SECT 1024
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/* Monitor at beginning of flash */
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
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#define CONFIG_SYS_MONITOR_LEN 0x40000 /* Reserve 256KiB */
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#define CONFIG_ENV_IS_IN_FLASH
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#define CONFIG_ENV_SECT_SIZE 0x20000
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#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
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#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x80000)
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/* Address and size of Redundant Environment Sector */
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#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
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#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
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/*-----------------------------------------------------------------------
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* CFI FLASH driver setup
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*/
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/* Flash memory is CFI compliant */
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#define CONFIG_SYS_FLASH_CFI
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/* Use drivers/cfi_flash.c */
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#define CONFIG_FLASH_CFI_DRIVER
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/* Use buffered writes (~10x faster) */
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#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
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/* Use hardware sector protection */
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#define CONFIG_SYS_FLASH_PROTECTION
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/*
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* Filesystem
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*/
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#define CONFIG_CMD_JFFS2
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#define CONFIG_CMD_UBI
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#define CONFIG_CMD_UBIFS
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#define CONFIG_RBTREE
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#define CONFIG_MTD_PARTITIONS
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#define CONFIG_CMD_MTDPARTS
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#define CONFIG_LZO
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#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
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#define CONFIG_FLASH_CFI_MTD
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#define MTDIDS_DEFAULT "nor0=physmap-flash.0," \
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"nand0=gen_nand"
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#define MTDPARTS_DEFAULT \
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"mtdparts=physmap-flash.0:" \
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"512k(U-Boot),128k(env1),128k(env2)," \
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"2304k(kernel),13m(ramdisk),-(user);" \
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"gen_nand:" \
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"128m(nand)"
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/* additions for new relocation code, must be added to all boards */
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#define CONFIG_SYS_SDRAM_BASE 0x80000000
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#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
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#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
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#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)
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#define CONFIG_BOARD_EARLY_INIT_F
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#endif /* __CONFIG_H */
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