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d08607e1e7
Add the definitions for the RDC mappings for i.MX6 SoloX. Signed-off-by: Ye.Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
155 lines
2.5 KiB
C
155 lines
2.5 KiB
C
/*
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* Copyright (C) 2014 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __MX6SX_RDC_H__
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#define __MX6SX_RDC_H__
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#define RDC_SEMA_PROC_ID 2 /* The processor ID for main CPU */
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enum {
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RDC_PER_PWM1 = 0,
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RDC_PER_PWM2,
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RDC_PER_PWM3,
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RDC_PER_PWM4,
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RDC_PER_CAN1,
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RDC_PER_CAN2,
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RDC_PER_GPT,
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RDC_PER_GPIO1,
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RDC_PER_GPIO2,
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RDC_PER_GPIO3,
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RDC_PER_GPIO4,
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RDC_PER_GPIO5,
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RDC_PER_GPIO6,
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RDC_PER_GPIO7,
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RDC_PER_KPP,
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RDC_PER_WDOG1,
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RDC_PER_WODG2,
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RDC_PER_CCM,
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RDC_PER_ANATOPDIG,
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RDC_PER_SNVSHP,
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RDC_PER_EPIT1,
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RDC_PER_EPIT2,
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RDC_PER_SRC,
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RDC_PER_GPC,
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RDC_PER_IOMUXC,
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RDC_PER_IOMUXCGPR,
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RDC_PER_CANFD1,
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RDC_PER_SDMA,
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RDC_PER_CANFD2,
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RDC_PER_SEMA1,
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RDC_PER_SEMA2,
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RDC_PER_RDC,
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RDC_PER_AIPSTZ1_GE1,
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RDC_PER_AIPSTZ2_GE2,
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RDC_PER_USBO2H_PL301,
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RDC_PER_USBO2H_USB,
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RDC_PER_ENET1,
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RDC_PER_MLB25,
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RDC_PER_USDHC1,
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RDC_PER_USDHC2,
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RDC_PER_USDHC3,
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RDC_PER_USDHC4,
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RDC_PER_I2C1,
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RDC_PER_I2C2,
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RDC_PER_I2C3,
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RDC_PER_ROMCP,
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RDC_PER_MMDC,
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RDC_PER_ENET2,
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RDC_PER_EIM,
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RDC_PER_OCOTP,
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RDC_PER_CSU,
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RDC_PER_PERFMON1,
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RDC_PER_PERFMON2,
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RDC_PER_AXIMON,
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RDC_PER_TZASC1,
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RDC_PER_SAI1,
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RDC_PER_AUDMUX,
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RDC_PER_SAI2,
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RDC_PER_QSPI1,
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RDC_PER_QSPI2,
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RDC_PER_UART2,
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RDC_PER_UART3,
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RDC_PER_UART4,
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RDC_PER_UART5,
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RDC_PER_I2C4,
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RDC_PER_QOSC,
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RDC_PER_CAAM,
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RDC_PER_DAP,
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RDC_PER_ADC1,
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RDC_PER_ADC2,
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RDC_PER_WDOG3,
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RDC_PER_ECSPI5,
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RDC_PER_SEMA4,
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RDC_PER_MUPORT1,
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RDC_PER_CANFD_CPU,
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RDC_PER_MUPORT2,
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RDC_PER_UART6,
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RDC_PER_PWM5,
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RDC_PER_PWM6,
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RDC_PER_PWM7,
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RDC_PER_PWM8,
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RDC_PER_AIPSTZ3_GE0,
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RDC_PER_AIPSTZ3_GE1,
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RDC_PER_RESERVED1,
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RDC_PER_SPDIF,
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RDC_PER_ECSPI1,
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RDC_PER_ECSPI2,
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RDC_PER_ECSPI3,
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RDC_PER_ECSPI4,
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RDC_PER_RESERVED2,
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RDC_PER_RESERVED3,
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RDC_PER_UART1,
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RDC_PER_ESAI,
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RDC_PER_SSI1,
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RDC_PER_SSI2,
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RDC_PER_SSI3,
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RDC_PER_ASRC,
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RDC_PER_RESERVED4,
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RDC_PER_SPBA_MA,
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RDC_PER_GIS,
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RDC_PER_DCIC1,
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RDC_PER_DCIC2,
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RDC_PER_CSI1,
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RDC_PER_PXP,
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RDC_PER_CSI2,
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RDC_PER_LCDIF1,
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RDC_PER_LCDIF2,
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RDC_PER_VADC,
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RDC_PER_VDEC,
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RDC_PER_SPBA_DISPLAYMIX,
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};
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enum {
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RDC_MA_A9_L2CACHE = 0,
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RDC_MA_M4,
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RDC_MA_GPU,
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RDC_MA_CSI1,
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RDC_MA_CSI2,
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RDC_MA_LCDIF1,
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RDC_MA_LCDIF2,
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RDC_MA_PXP,
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RDC_MA_PCIE_CTRL,
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RDC_MA_DAP,
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RDC_MA_CAAM,
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RDC_MA_SDMA_PERI,
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RDC_MA_SDMA_BURST,
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RDC_MA_APBHDMA,
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RDC_MA_RAWNAND,
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RDC_MA_USDHC1,
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RDC_MA_USDHC2,
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RDC_MA_USDHC3,
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RDC_MA_USDHC4,
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RDC_MA_USB,
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RDC_MA_MLB,
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RDC_MA_TEST,
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RDC_MA_ENET1_TX,
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RDC_MA_ENET1_RX,
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RDC_MA_ENET2_TX,
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RDC_MA_ENET2_RX,
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RDC_MA_SDMA,
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};
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#endif /* __MX6SX_RDC_H__*/
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