mirror of
https://github.com/AsahiLinux/u-boot
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3c1d218a1d
LS2080A is the primary SoC, and LS2085A is a personality with AIOP and DPAA DDR. The RDB and QDS boards support both personality. By detecting the SVR at runtime, a single image per board can support both SoCs. It gives users flexibility to swtich SoC without the need to reprogram the board. Signed-off-by: York Sun <york.sun@nxp.com> CC: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
694 lines
17 KiB
C
694 lines
17 KiB
C
/*
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* Copyright 2014-2015 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/errno.h>
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#include <asm/system.h>
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#include <asm/armv8/mmu.h>
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#include <asm/io.h>
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#include <asm/arch/fsl_serdes.h>
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#include <asm/arch/soc.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/speed.h>
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#ifdef CONFIG_MP
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#include <asm/arch/mp.h>
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#endif
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#include <fm_eth.h>
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#include <fsl_debug_server.h>
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#include <fsl-mc/fsl_mc.h>
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#ifdef CONFIG_FSL_ESDHC
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#include <fsl_esdhc.h>
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#endif
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DECLARE_GLOBAL_DATA_PTR;
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static struct mm_region layerscape_mem_map[] = {
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{
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/* List terminator */
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0,
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}
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};
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struct mm_region *mem_map = layerscape_mem_map;
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void cpu_name(char *name)
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{
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struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
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unsigned int i, svr, ver;
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svr = gur_in32(&gur->svr);
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ver = SVR_SOC_VER(svr);
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for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++)
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if ((cpu_type_list[i].soc_ver & SVR_WO_E) == ver) {
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strcpy(name, cpu_type_list[i].name);
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if (IS_E_PROCESSOR(svr))
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strcat(name, "E");
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break;
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}
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if (i == ARRAY_SIZE(cpu_type_list))
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strcpy(name, "unknown");
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}
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#ifndef CONFIG_SYS_DCACHE_OFF
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static void set_pgtable_section(u64 *page_table, u64 index, u64 section,
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u64 memory_type, u64 attribute)
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{
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u64 value;
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value = section | PTE_TYPE_BLOCK | PTE_BLOCK_AF;
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value |= PMD_ATTRINDX(memory_type);
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value |= attribute;
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page_table[index] = value;
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}
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static void set_pgtable_table(u64 *page_table, u64 index, u64 *table_addr)
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{
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u64 value;
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value = (u64)table_addr | PTE_TYPE_TABLE;
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page_table[index] = value;
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}
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/*
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* Set the block entries according to the information of the table.
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*/
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static int set_block_entry(const struct sys_mmu_table *list,
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struct table_info *table)
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{
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u64 block_size = 0, block_shift = 0;
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u64 block_addr, index;
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int j;
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if (table->entry_size == BLOCK_SIZE_L1) {
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block_size = BLOCK_SIZE_L1;
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block_shift = SECTION_SHIFT_L1;
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} else if (table->entry_size == BLOCK_SIZE_L2) {
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block_size = BLOCK_SIZE_L2;
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block_shift = SECTION_SHIFT_L2;
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} else {
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return -EINVAL;
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}
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block_addr = list->phys_addr;
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index = (list->virt_addr - table->table_base) >> block_shift;
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for (j = 0; j < (list->size >> block_shift); j++) {
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set_pgtable_section(table->ptr,
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index,
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block_addr,
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list->memory_type,
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list->attribute);
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block_addr += block_size;
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index++;
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}
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return 0;
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}
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/*
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* Find the corresponding table entry for the list.
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*/
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static int find_table(const struct sys_mmu_table *list,
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struct table_info *table, u64 *level0_table)
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{
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u64 index = 0, level = 0;
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u64 *level_table = level0_table;
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u64 temp_base = 0, block_size = 0, block_shift = 0;
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while (level < 3) {
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if (level == 0) {
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block_size = BLOCK_SIZE_L0;
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block_shift = SECTION_SHIFT_L0;
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} else if (level == 1) {
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block_size = BLOCK_SIZE_L1;
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block_shift = SECTION_SHIFT_L1;
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} else if (level == 2) {
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block_size = BLOCK_SIZE_L2;
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block_shift = SECTION_SHIFT_L2;
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}
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index = 0;
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while (list->virt_addr >= temp_base) {
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index++;
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temp_base += block_size;
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}
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temp_base -= block_size;
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if ((level_table[index - 1] & PTE_TYPE_MASK) ==
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PTE_TYPE_TABLE) {
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level_table = (u64 *)(level_table[index - 1] &
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~PTE_TYPE_MASK);
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level++;
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continue;
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} else {
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if (level == 0)
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return -EINVAL;
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if ((list->phys_addr + list->size) >
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(temp_base + block_size * NUM_OF_ENTRY))
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return -EINVAL;
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/*
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* Check the address and size of the list member is
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* aligned with the block size.
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*/
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if (((list->phys_addr & (block_size - 1)) != 0) ||
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((list->size & (block_size - 1)) != 0))
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return -EINVAL;
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table->ptr = level_table;
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table->table_base = temp_base -
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((index - 1) << block_shift);
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table->entry_size = block_size;
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return 0;
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}
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}
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return -EINVAL;
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}
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/*
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* To start MMU before DDR is available, we create MMU table in SRAM.
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* The base address of SRAM is CONFIG_SYS_FSL_OCRAM_BASE. We use three
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* levels of translation tables here to cover 40-bit address space.
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* We use 4KB granule size, with 40 bits physical address, T0SZ=24
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* Level 0 IA[39], table address @0
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* Level 1 IA[38:30], table address @0x1000, 0x2000
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* Level 2 IA[29:21], table address @0x3000, 0x4000
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* Address above 0x5000 is free for other purpose.
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*/
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static inline void early_mmu_setup(void)
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{
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unsigned int el, i;
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u64 *level0_table = (u64 *)CONFIG_SYS_FSL_OCRAM_BASE;
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u64 *level1_table0 = (u64 *)(CONFIG_SYS_FSL_OCRAM_BASE + 0x1000);
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u64 *level1_table1 = (u64 *)(CONFIG_SYS_FSL_OCRAM_BASE + 0x2000);
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u64 *level2_table0 = (u64 *)(CONFIG_SYS_FSL_OCRAM_BASE + 0x3000);
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u64 *level2_table1 = (u64 *)(CONFIG_SYS_FSL_OCRAM_BASE + 0x4000);
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struct table_info table = {level0_table, 0, BLOCK_SIZE_L0};
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/* Invalidate all table entries */
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memset(level0_table, 0, 0x5000);
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/* Fill in the table entries */
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set_pgtable_table(level0_table, 0, level1_table0);
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set_pgtable_table(level0_table, 1, level1_table1);
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set_pgtable_table(level1_table0, 0, level2_table0);
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#ifdef CONFIG_FSL_LSCH3
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set_pgtable_table(level1_table0,
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CONFIG_SYS_FLASH_BASE >> SECTION_SHIFT_L1,
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level2_table1);
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#elif defined(CONFIG_FSL_LSCH2)
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set_pgtable_table(level1_table0, 1, level2_table1);
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#endif
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/* Find the table and fill in the block entries */
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for (i = 0; i < ARRAY_SIZE(early_mmu_table); i++) {
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if (find_table(&early_mmu_table[i],
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&table, level0_table) == 0) {
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/*
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* If find_table() returns error, it cannot be dealt
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* with here. Breakpoint can be added for debugging.
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*/
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set_block_entry(&early_mmu_table[i], &table);
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/*
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* If set_block_entry() returns error, it cannot be
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* dealt with here too.
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*/
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}
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}
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el = current_el();
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set_ttbr_tcr_mair(el, (u64)level0_table, LAYERSCAPE_TCR,
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MEMORY_ATTRIBUTES);
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set_sctlr(get_sctlr() | CR_M);
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}
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#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
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/*
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* Called from final mmu setup. The phys_addr is new, non-existing
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* address. A new sub table is created @level2_table_secure to cover
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* size of CONFIG_SYS_MEM_RESERVE_SECURE memory.
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*/
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static inline int final_secure_ddr(u64 *level0_table,
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u64 *level2_table_secure,
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phys_addr_t phys_addr)
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{
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int ret = -EINVAL;
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struct table_info table = {};
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struct sys_mmu_table ddr_entry = {
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0, 0, BLOCK_SIZE_L1, MT_NORMAL,
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PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
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};
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u64 index;
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/* Need to create a new table */
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ddr_entry.virt_addr = phys_addr & ~(BLOCK_SIZE_L1 - 1);
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ddr_entry.phys_addr = phys_addr & ~(BLOCK_SIZE_L1 - 1);
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ret = find_table(&ddr_entry, &table, level0_table);
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if (ret)
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return ret;
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index = (ddr_entry.virt_addr - table.table_base) >> SECTION_SHIFT_L1;
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set_pgtable_table(table.ptr, index, level2_table_secure);
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table.ptr = level2_table_secure;
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table.table_base = ddr_entry.virt_addr;
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table.entry_size = BLOCK_SIZE_L2;
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ret = set_block_entry(&ddr_entry, &table);
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if (ret) {
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printf("MMU error: could not fill non-secure ddr block entries\n");
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return ret;
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}
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ddr_entry.virt_addr = phys_addr;
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ddr_entry.phys_addr = phys_addr;
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ddr_entry.size = CONFIG_SYS_MEM_RESERVE_SECURE;
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ddr_entry.attribute = PTE_BLOCK_OUTER_SHARE;
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ret = find_table(&ddr_entry, &table, level0_table);
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if (ret) {
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printf("MMU error: could not find secure ddr table\n");
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return ret;
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}
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ret = set_block_entry(&ddr_entry, &table);
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if (ret)
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printf("MMU error: could not set secure ddr block entry\n");
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return ret;
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}
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#endif
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/*
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* The final tables look similar to early tables, but different in detail.
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* These tables are in DRAM. Sub tables are added to enable cache for
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* QBMan and OCRAM.
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*
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* Put the MMU table in secure memory if gd->secure_ram is valid.
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* OCRAM will be not used for this purpose so gd->secure_ram can't be 0.
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*
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* Level 1 table 0 contains 512 entries for each 1GB from 0 to 512GB.
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* Level 1 table 1 contains 512 entries for each 1GB from 512GB to 1TB.
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* Level 2 table 0 contains 512 entries for each 2MB from 0 to 1GB.
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*
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* For LSCH3:
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* Level 2 table 1 contains 512 entries for each 2MB from 32GB to 33GB.
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* For LSCH2:
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* Level 2 table 1 contains 512 entries for each 2MB from 1GB to 2GB.
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* Level 2 table 2 contains 512 entries for each 2MB from 20GB to 21GB.
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*/
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static inline void final_mmu_setup(void)
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{
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unsigned int el = current_el();
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unsigned int i;
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u64 *level0_table = (u64 *)gd->arch.tlb_addr;
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u64 *level1_table0;
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u64 *level1_table1;
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u64 *level2_table0;
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u64 *level2_table1;
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#ifdef CONFIG_FSL_LSCH2
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u64 *level2_table2;
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#endif
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struct table_info table = {NULL, 0, BLOCK_SIZE_L0};
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#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
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u64 *level2_table_secure;
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if (el == 3) {
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/*
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* Only use gd->secure_ram if the address is recalculated
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* Align to 4KB for MMU table
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*/
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if (gd->secure_ram & MEM_RESERVE_SECURE_MAINTAINED)
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level0_table = (u64 *)(gd->secure_ram & ~0xfff);
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else
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printf("MMU warning: gd->secure_ram is not maintained, disabled.\n");
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}
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#endif
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level1_table0 = level0_table + 512;
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level1_table1 = level1_table0 + 512;
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level2_table0 = level1_table1 + 512;
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level2_table1 = level2_table0 + 512;
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#ifdef CONFIG_FSL_LSCH2
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level2_table2 = level2_table1 + 512;
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#endif
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table.ptr = level0_table;
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/* Invalidate all table entries */
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memset(level0_table, 0, PGTABLE_SIZE);
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/* Fill in the table entries */
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set_pgtable_table(level0_table, 0, level1_table0);
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set_pgtable_table(level0_table, 1, level1_table1);
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set_pgtable_table(level1_table0, 0, level2_table0);
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#ifdef CONFIG_FSL_LSCH3
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set_pgtable_table(level1_table0,
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CONFIG_SYS_FSL_QBMAN_BASE >> SECTION_SHIFT_L1,
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level2_table1);
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#elif defined(CONFIG_FSL_LSCH2)
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set_pgtable_table(level1_table0, 1, level2_table1);
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set_pgtable_table(level1_table0,
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CONFIG_SYS_FSL_QBMAN_BASE >> SECTION_SHIFT_L1,
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level2_table2);
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#endif
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/* Find the table and fill in the block entries */
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for (i = 0; i < ARRAY_SIZE(final_mmu_table); i++) {
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if (find_table(&final_mmu_table[i],
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&table, level0_table) == 0) {
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if (set_block_entry(&final_mmu_table[i],
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&table) != 0) {
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printf("MMU error: could not set block entry for %p\n",
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&final_mmu_table[i]);
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}
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} else {
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printf("MMU error: could not find the table for %p\n",
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&final_mmu_table[i]);
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}
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}
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/* Set the secure memory to secure in MMU */
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#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
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if (el == 3 && gd->secure_ram & MEM_RESERVE_SECURE_MAINTAINED) {
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#ifdef CONFIG_FSL_LSCH3
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level2_table_secure = level2_table1 + 512;
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#elif defined(CONFIG_FSL_LSCH2)
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level2_table_secure = level2_table2 + 512;
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#endif
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if (!final_secure_ddr(level0_table,
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level2_table_secure,
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gd->secure_ram & ~0x3)) {
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gd->secure_ram |= MEM_RESERVE_SECURE_SECURED;
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debug("Now MMU table is in secured memory at 0x%llx\n",
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gd->secure_ram & ~0x3);
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} else {
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printf("MMU warning: Failed to secure DDR\n");
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}
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}
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#endif
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/* flush new MMU table */
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flush_dcache_range((ulong)level0_table,
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(ulong)level0_table + gd->arch.tlb_size);
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#ifdef CONFIG_SYS_DPAA_FMAN
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flush_dcache_all();
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#endif
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/* point TTBR to the new table */
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set_ttbr_tcr_mair(el, (u64)level0_table, LAYERSCAPE_TCR_FINAL,
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MEMORY_ATTRIBUTES);
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/*
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* MMU is already enabled, just need to invalidate TLB to load the
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* new table. The new table is compatible with the current table, if
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* MMU somehow walks through the new table before invalidation TLB,
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* it still works. So we don't need to turn off MMU here.
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*/
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}
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u64 get_page_table_size(void)
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{
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return 0x10000;
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}
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int arch_cpu_init(void)
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{
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icache_enable();
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__asm_invalidate_dcache_all();
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__asm_invalidate_tlb_all();
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early_mmu_setup();
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set_sctlr(get_sctlr() | CR_C);
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return 0;
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}
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/*
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* This function is called from lib/board.c.
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* It recreates MMU table in main memory. MMU and d-cache are enabled earlier.
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* There is no need to disable d-cache for this operation.
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*/
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void enable_caches(void)
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{
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final_mmu_setup();
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__asm_invalidate_tlb_all();
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}
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#endif
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static inline u32 initiator_type(u32 cluster, int init_id)
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{
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struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
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u32 idx = (cluster >> (init_id * 8)) & TP_CLUSTER_INIT_MASK;
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u32 type = 0;
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type = gur_in32(&gur->tp_ityp[idx]);
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if (type & TP_ITYP_AV)
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return type;
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return 0;
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}
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u32 cpu_mask(void)
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{
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struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
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int i = 0, count = 0;
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u32 cluster, type, mask = 0;
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do {
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int j;
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cluster = gur_in32(&gur->tp_cluster[i].lower);
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for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
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type = initiator_type(cluster, j);
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if (type) {
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if (TP_ITYP_TYPE(type) == TP_ITYP_TYPE_ARM)
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mask |= 1 << count;
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count++;
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}
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}
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i++;
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} while ((cluster & TP_CLUSTER_EOC) == 0x0);
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return mask;
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}
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/*
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* Return the number of cores on this SOC.
|
|
*/
|
|
int cpu_numcores(void)
|
|
{
|
|
return hweight32(cpu_mask());
|
|
}
|
|
|
|
int fsl_qoriq_core_to_cluster(unsigned int core)
|
|
{
|
|
struct ccsr_gur __iomem *gur =
|
|
(void __iomem *)(CONFIG_SYS_FSL_GUTS_ADDR);
|
|
int i = 0, count = 0;
|
|
u32 cluster;
|
|
|
|
do {
|
|
int j;
|
|
|
|
cluster = gur_in32(&gur->tp_cluster[i].lower);
|
|
for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
|
|
if (initiator_type(cluster, j)) {
|
|
if (count == core)
|
|
return i;
|
|
count++;
|
|
}
|
|
}
|
|
i++;
|
|
} while ((cluster & TP_CLUSTER_EOC) == 0x0);
|
|
|
|
return -1; /* cannot identify the cluster */
|
|
}
|
|
|
|
u32 fsl_qoriq_core_to_type(unsigned int core)
|
|
{
|
|
struct ccsr_gur __iomem *gur =
|
|
(void __iomem *)(CONFIG_SYS_FSL_GUTS_ADDR);
|
|
int i = 0, count = 0;
|
|
u32 cluster, type;
|
|
|
|
do {
|
|
int j;
|
|
|
|
cluster = gur_in32(&gur->tp_cluster[i].lower);
|
|
for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
|
|
type = initiator_type(cluster, j);
|
|
if (type) {
|
|
if (count == core)
|
|
return type;
|
|
count++;
|
|
}
|
|
}
|
|
i++;
|
|
} while ((cluster & TP_CLUSTER_EOC) == 0x0);
|
|
|
|
return -1; /* cannot identify the cluster */
|
|
}
|
|
|
|
#ifdef CONFIG_DISPLAY_CPUINFO
|
|
int print_cpuinfo(void)
|
|
{
|
|
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
|
|
struct sys_info sysinfo;
|
|
char buf[32];
|
|
unsigned int i, core;
|
|
u32 type, rcw, svr = gur_in32(&gur->svr);
|
|
|
|
puts("SoC: ");
|
|
|
|
cpu_name(buf);
|
|
printf(" %s (0x%x)\n", buf, svr);
|
|
memset((u8 *)buf, 0x00, ARRAY_SIZE(buf));
|
|
get_sys_info(&sysinfo);
|
|
puts("Clock Configuration:");
|
|
for_each_cpu(i, core, cpu_numcores(), cpu_mask()) {
|
|
if (!(i % 3))
|
|
puts("\n ");
|
|
type = TP_ITYP_VER(fsl_qoriq_core_to_type(core));
|
|
printf("CPU%d(%s):%-4s MHz ", core,
|
|
type == TY_ITYP_VER_A7 ? "A7 " :
|
|
(type == TY_ITYP_VER_A53 ? "A53" :
|
|
(type == TY_ITYP_VER_A57 ? "A57" : " ")),
|
|
strmhz(buf, sysinfo.freq_processor[core]));
|
|
}
|
|
printf("\n Bus: %-4s MHz ",
|
|
strmhz(buf, sysinfo.freq_systembus));
|
|
printf("DDR: %-4s MT/s", strmhz(buf, sysinfo.freq_ddrbus));
|
|
#ifdef CONFIG_SYS_DPAA_FMAN
|
|
printf(" FMAN: %-4s MHz", strmhz(buf, sysinfo.freq_fman[0]));
|
|
#endif
|
|
#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
|
|
if (soc_has_dp_ddr()) {
|
|
printf(" DP-DDR: %-4s MT/s",
|
|
strmhz(buf, sysinfo.freq_ddrbus2));
|
|
}
|
|
#endif
|
|
puts("\n");
|
|
|
|
/*
|
|
* Display the RCW, so that no one gets confused as to what RCW
|
|
* we're actually using for this boot.
|
|
*/
|
|
puts("Reset Configuration Word (RCW):");
|
|
for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) {
|
|
rcw = gur_in32(&gur->rcwsr[i]);
|
|
if ((i % 4) == 0)
|
|
printf("\n %08x:", i * 4);
|
|
printf(" %08x", rcw);
|
|
}
|
|
puts("\n");
|
|
|
|
return 0;
|
|
}
|
|
#endif
|
|
|
|
#ifdef CONFIG_FSL_ESDHC
|
|
int cpu_mmc_init(bd_t *bis)
|
|
{
|
|
return fsl_esdhc_mmc_init(bis);
|
|
}
|
|
#endif
|
|
|
|
int cpu_eth_init(bd_t *bis)
|
|
{
|
|
int error = 0;
|
|
|
|
#ifdef CONFIG_FSL_MC_ENET
|
|
error = fsl_mc_ldpaa_init(bis);
|
|
#endif
|
|
#ifdef CONFIG_FMAN_ENET
|
|
fm_standard_init(bis);
|
|
#endif
|
|
return error;
|
|
}
|
|
|
|
int arch_early_init_r(void)
|
|
{
|
|
#ifdef CONFIG_MP
|
|
int rv = 1;
|
|
#endif
|
|
|
|
#ifdef CONFIG_SYS_FSL_ERRATUM_A009635
|
|
erratum_a009635();
|
|
#endif
|
|
|
|
#ifdef CONFIG_MP
|
|
rv = fsl_layerscape_wake_seconday_cores();
|
|
if (rv)
|
|
printf("Did not wake secondary cores\n");
|
|
#endif
|
|
|
|
#ifdef CONFIG_SYS_HAS_SERDES
|
|
fsl_serdes_init();
|
|
#endif
|
|
#ifdef CONFIG_FMAN_ENET
|
|
fman_enet_init();
|
|
#endif
|
|
return 0;
|
|
}
|
|
|
|
int timer_init(void)
|
|
{
|
|
u32 __iomem *cntcr = (u32 *)CONFIG_SYS_FSL_TIMER_ADDR;
|
|
#ifdef CONFIG_FSL_LSCH3
|
|
u32 __iomem *cltbenr = (u32 *)CONFIG_SYS_FSL_PMU_CLTBENR;
|
|
#endif
|
|
#ifdef COUNTER_FREQUENCY_REAL
|
|
unsigned long cntfrq = COUNTER_FREQUENCY_REAL;
|
|
|
|
/* Update with accurate clock frequency */
|
|
asm volatile("msr cntfrq_el0, %0" : : "r" (cntfrq) : "memory");
|
|
#endif
|
|
|
|
#ifdef CONFIG_FSL_LSCH3
|
|
/* Enable timebase for all clusters.
|
|
* It is safe to do so even some clusters are not enabled.
|
|
*/
|
|
out_le32(cltbenr, 0xf);
|
|
#endif
|
|
|
|
/* Enable clock for timer
|
|
* This is a global setting.
|
|
*/
|
|
out_le32(cntcr, 0x1);
|
|
|
|
return 0;
|
|
}
|
|
|
|
void reset_cpu(ulong addr)
|
|
{
|
|
u32 __iomem *rstcr = (u32 *)CONFIG_SYS_FSL_RST_ADDR;
|
|
u32 val;
|
|
|
|
/* Raise RESET_REQ_B */
|
|
val = scfg_in32(rstcr);
|
|
val |= 0x02;
|
|
scfg_out32(rstcr, val);
|
|
}
|
|
|
|
phys_size_t board_reserve_ram_top(phys_size_t ram_size)
|
|
{
|
|
phys_size_t ram_top = ram_size;
|
|
|
|
#ifdef CONFIG_SYS_MEM_TOP_HIDE
|
|
#error CONFIG_SYS_MEM_TOP_HIDE not to be used together with this function
|
|
#endif
|
|
/* Carve the Debug Server private DRAM block from the end of DRAM */
|
|
#ifdef CONFIG_FSL_DEBUG_SERVER
|
|
ram_top -= debug_server_get_dram_block_size();
|
|
#endif
|
|
|
|
/* Carve the MC private DRAM block from the end of DRAM */
|
|
#ifdef CONFIG_FSL_MC_ENET
|
|
ram_top -= mc_get_dram_block_size();
|
|
ram_top &= ~(CONFIG_SYS_MC_RSV_MEM_ALIGN - 1);
|
|
#endif
|
|
|
|
return ram_top;
|
|
}
|