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u-boot/drivers/clk/rockchip
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Philipp Tomsich ddfe77df15 rockchip: clk: rk3368: implement bandwidth adjust for PLLs 
The RK3368 TRM recommends to configure the bandwith adjustment (CON2)
for PLLs to NF/2.  This implements this for all reconfigurations of
PLLs and removes the 'has_bwadj' flag (as the RK3368 always has the
bandwidth-adjustment feature according to its manual).

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-13 17:12:28 +02:00
..
clk_rk322x.c rockchip: rk322x: add clock driver 2017-07-11 12:13:45 +02:00
clk_rk3036.c rockchip: clk: rk3036: correct setting for pll integer mode 2017-06-23 16:40:23 +02:00
clk_rk3188.c dm: Rename dev_addr..() functions 2017-06-01 07:03:01 -06:00
clk_rk3288.c rockchip: Init clocks again when chain-loading 2017-06-09 13:45:33 -06:00
clk_rk3328.c dm: Rename dev_addr..() functions 2017-06-01 07:03:01 -06:00
clk_rk3368.c rockchip: clk: rk3368: implement bandwidth adjust for PLLs 2017-08-13 17:12:28 +02:00
clk_rk3399.c dm: Rename dev_addr..() functions 2017-06-01 07:03:01 -06:00
clk_rv1108.c clk_rv1108.c: Fix unused variable warning 2017-06-23 10:38:05 -04:00
Makefile rockchip: rk322x: add clock driver 2017-07-11 12:13:45 +02:00