mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-30 08:31:03 +00:00
4e7f8de426
- Use - instead of @ for OPP tables - Add input-delay properties to Cadence eMMC nodes - Restore full license text because code-diff is annoying - Fix NAND compatible strings Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
434 lines
11 KiB
Text
434 lines
11 KiB
Text
/*
|
|
* Device Tree Source for UniPhier LD11 SoC
|
|
*
|
|
* Copyright (C) 2016 Socionext Inc.
|
|
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
|
|
*
|
|
* This file is dual-licensed: you can use it either under the terms
|
|
* of the GPL or the X11 license, at your option. Note that this dual
|
|
* licensing only applies to this file, and not this project as a
|
|
* whole.
|
|
*
|
|
* a) This file is free software; you can redistribute it and/or
|
|
* modify it under the terms of the GNU General Public License as
|
|
* published by the Free Software Foundation; either version 2 of the
|
|
* License, or (at your option) any later version.
|
|
*
|
|
* This file is distributed in the hope that it will be useful,
|
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
* GNU General Public License for more details.
|
|
*
|
|
* Or, alternatively,
|
|
*
|
|
* b) Permission is hereby granted, free of charge, to any person
|
|
* obtaining a copy of this software and associated documentation
|
|
* files (the "Software"), to deal in the Software without
|
|
* restriction, including without limitation the rights to use,
|
|
* copy, modify, merge, publish, distribute, sublicense, and/or
|
|
* sell copies of the Software, and to permit persons to whom the
|
|
* Software is furnished to do so, subject to the following
|
|
* conditions:
|
|
*
|
|
* The above copyright notice and this permission notice shall be
|
|
* included in all copies or substantial portions of the Software.
|
|
*
|
|
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
|
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
|
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
|
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
|
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
|
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
|
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
|
* OTHER DEALINGS IN THE SOFTWARE.
|
|
*/
|
|
|
|
/memreserve/ 0x80000000 0x00080000;
|
|
|
|
/ {
|
|
compatible = "socionext,uniphier-ld11";
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
interrupt-parent = <&gic>;
|
|
|
|
cpus {
|
|
#address-cells = <2>;
|
|
#size-cells = <0>;
|
|
|
|
cpu-map {
|
|
cluster0 {
|
|
core0 {
|
|
cpu = <&cpu0>;
|
|
};
|
|
core1 {
|
|
cpu = <&cpu1>;
|
|
};
|
|
};
|
|
};
|
|
|
|
cpu0: cpu@0 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a53", "arm,armv8";
|
|
reg = <0 0x000>;
|
|
clocks = <&sys_clk 33>;
|
|
enable-method = "psci";
|
|
operating-points-v2 = <&cluster0_opp>;
|
|
};
|
|
|
|
cpu1: cpu@1 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a53", "arm,armv8";
|
|
reg = <0 0x001>;
|
|
clocks = <&sys_clk 33>;
|
|
enable-method = "psci";
|
|
operating-points-v2 = <&cluster0_opp>;
|
|
};
|
|
};
|
|
|
|
cluster0_opp: opp_table {
|
|
compatible = "operating-points-v2";
|
|
opp-shared;
|
|
|
|
opp-245000000 {
|
|
opp-hz = /bits/ 64 <245000000>;
|
|
clock-latency-ns = <300>;
|
|
};
|
|
opp-250000000 {
|
|
opp-hz = /bits/ 64 <250000000>;
|
|
clock-latency-ns = <300>;
|
|
};
|
|
opp-490000000 {
|
|
opp-hz = /bits/ 64 <490000000>;
|
|
clock-latency-ns = <300>;
|
|
};
|
|
opp-500000000 {
|
|
opp-hz = /bits/ 64 <500000000>;
|
|
clock-latency-ns = <300>;
|
|
};
|
|
opp-653334000 {
|
|
opp-hz = /bits/ 64 <653334000>;
|
|
clock-latency-ns = <300>;
|
|
};
|
|
opp-666667000 {
|
|
opp-hz = /bits/ 64 <666667000>;
|
|
clock-latency-ns = <300>;
|
|
};
|
|
opp-980000000 {
|
|
opp-hz = /bits/ 64 <980000000>;
|
|
clock-latency-ns = <300>;
|
|
};
|
|
};
|
|
|
|
psci {
|
|
compatible = "arm,psci-1.0";
|
|
method = "smc";
|
|
};
|
|
|
|
clocks {
|
|
refclk: ref {
|
|
compatible = "fixed-clock";
|
|
#clock-cells = <0>;
|
|
clock-frequency = <25000000>;
|
|
};
|
|
};
|
|
|
|
timer {
|
|
compatible = "arm,armv8-timer";
|
|
interrupts = <1 13 4>,
|
|
<1 14 4>,
|
|
<1 11 4>,
|
|
<1 10 4>;
|
|
};
|
|
|
|
soc@0 {
|
|
compatible = "simple-bus";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0 0 0 0xffffffff>;
|
|
u-boot,dm-pre-reloc;
|
|
|
|
serial0: serial@54006800 {
|
|
compatible = "socionext,uniphier-uart";
|
|
status = "disabled";
|
|
reg = <0x54006800 0x40>;
|
|
interrupts = <0 33 4>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_uart0>;
|
|
clocks = <&peri_clk 0>;
|
|
clock-frequency = <58820000>;
|
|
};
|
|
|
|
serial1: serial@54006900 {
|
|
compatible = "socionext,uniphier-uart";
|
|
status = "disabled";
|
|
reg = <0x54006900 0x40>;
|
|
interrupts = <0 35 4>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_uart1>;
|
|
clocks = <&peri_clk 1>;
|
|
clock-frequency = <58820000>;
|
|
};
|
|
|
|
serial2: serial@54006a00 {
|
|
compatible = "socionext,uniphier-uart";
|
|
status = "disabled";
|
|
reg = <0x54006a00 0x40>;
|
|
interrupts = <0 37 4>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_uart2>;
|
|
clocks = <&peri_clk 2>;
|
|
clock-frequency = <58820000>;
|
|
};
|
|
|
|
serial3: serial@54006b00 {
|
|
compatible = "socionext,uniphier-uart";
|
|
status = "disabled";
|
|
reg = <0x54006b00 0x40>;
|
|
interrupts = <0 177 4>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_uart3>;
|
|
clocks = <&peri_clk 3>;
|
|
clock-frequency = <58820000>;
|
|
};
|
|
|
|
i2c0: i2c@58780000 {
|
|
compatible = "socionext,uniphier-fi2c";
|
|
status = "disabled";
|
|
reg = <0x58780000 0x80>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
interrupts = <0 41 4>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_i2c0>;
|
|
clocks = <&peri_clk 4>;
|
|
clock-frequency = <100000>;
|
|
};
|
|
|
|
i2c1: i2c@58781000 {
|
|
compatible = "socionext,uniphier-fi2c";
|
|
status = "disabled";
|
|
reg = <0x58781000 0x80>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
interrupts = <0 42 4>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_i2c1>;
|
|
clocks = <&peri_clk 5>;
|
|
clock-frequency = <100000>;
|
|
};
|
|
|
|
i2c2: i2c@58782000 {
|
|
compatible = "socionext,uniphier-fi2c";
|
|
reg = <0x58782000 0x80>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
interrupts = <0 43 4>;
|
|
clocks = <&peri_clk 6>;
|
|
clock-frequency = <400000>;
|
|
};
|
|
|
|
i2c3: i2c@58783000 {
|
|
compatible = "socionext,uniphier-fi2c";
|
|
status = "disabled";
|
|
reg = <0x58783000 0x80>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
interrupts = <0 44 4>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_i2c3>;
|
|
clocks = <&peri_clk 7>;
|
|
clock-frequency = <100000>;
|
|
};
|
|
|
|
i2c4: i2c@58784000 {
|
|
compatible = "socionext,uniphier-fi2c";
|
|
status = "disabled";
|
|
reg = <0x58784000 0x80>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
interrupts = <0 45 4>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_i2c4>;
|
|
clocks = <&peri_clk 8>;
|
|
clock-frequency = <100000>;
|
|
};
|
|
|
|
i2c5: i2c@58785000 {
|
|
compatible = "socionext,uniphier-fi2c";
|
|
reg = <0x58785000 0x80>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
interrupts = <0 25 4>;
|
|
clocks = <&peri_clk 9>;
|
|
clock-frequency = <400000>;
|
|
};
|
|
|
|
system_bus: system-bus@58c00000 {
|
|
compatible = "socionext,uniphier-system-bus";
|
|
status = "disabled";
|
|
reg = <0x58c00000 0x400>;
|
|
#address-cells = <2>;
|
|
#size-cells = <1>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_system_bus>;
|
|
};
|
|
|
|
smpctrl@59800000 {
|
|
compatible = "socionext,uniphier-smpctrl";
|
|
reg = <0x59801000 0x400>;
|
|
};
|
|
|
|
sdctrl@59810000 {
|
|
compatible = "socionext,uniphier-ld11-sdctrl",
|
|
"simple-mfd", "syscon";
|
|
reg = <0x59810000 0x400>;
|
|
|
|
sd_rst: reset {
|
|
compatible = "socionext,uniphier-ld11-sd-reset";
|
|
#reset-cells = <1>;
|
|
};
|
|
};
|
|
|
|
perictrl@59820000 {
|
|
compatible = "socionext,uniphier-ld11-perictrl",
|
|
"simple-mfd", "syscon";
|
|
reg = <0x59820000 0x200>;
|
|
|
|
peri_clk: clock {
|
|
compatible = "socionext,uniphier-ld11-peri-clock";
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
peri_rst: reset {
|
|
compatible = "socionext,uniphier-ld11-peri-reset";
|
|
#reset-cells = <1>;
|
|
};
|
|
};
|
|
|
|
emmc: sdhc@5a000000 {
|
|
compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
|
|
reg = <0x5a000000 0x400>;
|
|
interrupts = <0 78 4>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_emmc_1v8>;
|
|
clocks = <&sys_clk 4>;
|
|
bus-width = <8>;
|
|
mmc-ddr-1_8v;
|
|
mmc-hs200-1_8v;
|
|
cdns,phy-input-delay-legacy = <4>;
|
|
cdns,phy-input-delay-mmc-highspeed = <2>;
|
|
cdns,phy-input-delay-mmc-ddr = <3>;
|
|
cdns,phy-dll-delay-sdclk = <21>;
|
|
cdns,phy-dll-delay-sdclk-hsmmc = <21>;
|
|
};
|
|
|
|
usb0: usb@5a800100 {
|
|
compatible = "socionext,uniphier-ehci", "generic-ehci";
|
|
status = "disabled";
|
|
reg = <0x5a800100 0x100>;
|
|
interrupts = <0 243 4>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_usb0>;
|
|
clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>;
|
|
resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
|
|
<&mio_rst 12>;
|
|
};
|
|
|
|
usb1: usb@5a810100 {
|
|
compatible = "socionext,uniphier-ehci", "generic-ehci";
|
|
status = "disabled";
|
|
reg = <0x5a810100 0x100>;
|
|
interrupts = <0 244 4>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_usb1>;
|
|
clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>;
|
|
resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
|
|
<&mio_rst 13>;
|
|
};
|
|
|
|
usb2: usb@5a820100 {
|
|
compatible = "socionext,uniphier-ehci", "generic-ehci";
|
|
status = "disabled";
|
|
reg = <0x5a820100 0x100>;
|
|
interrupts = <0 245 4>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_usb2>;
|
|
clocks = <&mio_clk 7>, <&mio_clk 10>, <&mio_clk 14>;
|
|
resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>,
|
|
<&mio_rst 14>;
|
|
};
|
|
|
|
mioctrl@5b3e0000 {
|
|
compatible = "socionext,uniphier-ld11-mioctrl",
|
|
"simple-mfd", "syscon";
|
|
reg = <0x5b3e0000 0x800>;
|
|
|
|
mio_clk: clock {
|
|
compatible = "socionext,uniphier-ld11-mio-clock";
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
mio_rst: reset {
|
|
compatible = "socionext,uniphier-ld11-mio-reset";
|
|
#reset-cells = <1>;
|
|
resets = <&sys_rst 7>;
|
|
};
|
|
};
|
|
|
|
soc-glue@5f800000 {
|
|
compatible = "socionext,uniphier-ld11-soc-glue",
|
|
"simple-mfd", "syscon";
|
|
reg = <0x5f800000 0x2000>;
|
|
u-boot,dm-pre-reloc;
|
|
|
|
pinctrl: pinctrl {
|
|
compatible = "socionext,uniphier-ld11-pinctrl";
|
|
u-boot,dm-pre-reloc;
|
|
};
|
|
};
|
|
|
|
aidet@5fc20000 {
|
|
compatible = "simple-mfd", "syscon";
|
|
reg = <0x5fc20000 0x200>;
|
|
};
|
|
|
|
gic: interrupt-controller@5fe00000 {
|
|
compatible = "arm,gic-v3";
|
|
reg = <0x5fe00000 0x10000>, /* GICD */
|
|
<0x5fe40000 0x80000>; /* GICR */
|
|
interrupt-controller;
|
|
#interrupt-cells = <3>;
|
|
interrupts = <1 9 4>;
|
|
};
|
|
|
|
sysctrl@61840000 {
|
|
compatible = "socionext,uniphier-ld11-sysctrl",
|
|
"simple-mfd", "syscon";
|
|
reg = <0x61840000 0x10000>;
|
|
|
|
sys_clk: clock {
|
|
compatible = "socionext,uniphier-ld11-clock";
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
sys_rst: reset {
|
|
compatible = "socionext,uniphier-ld11-reset";
|
|
#reset-cells = <1>;
|
|
};
|
|
};
|
|
|
|
nand: nand@68000000 {
|
|
compatible = "socionext,uniphier-denali-nand-v5b";
|
|
status = "disabled";
|
|
reg-names = "nand_data", "denali_reg";
|
|
reg = <0x68000000 0x20>, <0x68100000 0x1000>;
|
|
interrupts = <0 65 4>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_nand>;
|
|
clocks = <&sys_clk 2>;
|
|
nand-ecc-strength = <8>;
|
|
};
|
|
};
|
|
};
|
|
|
|
/include/ "uniphier-pinctrl.dtsi"
|