mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-16 17:58:23 +00:00
262 lines
6.7 KiB
C
262 lines
6.7 KiB
C
/*
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* (C) Copyright 2005
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* Sangmoon Kim, dogoil@etinsys.com.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#define CONFIG_MPC824X 1
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#define CONFIG_MPC8245 1
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#define CONFIG_KVME080 1
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#define CONFIG_CONS_INDEX 1
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#define CONFIG_BAUDRATE 115200
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#define CONFIG_BOOTDELAY 5
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#define CONFIG_IPADDR 192.168.0.2
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#define CONFIG_NETMASK 255.255.255.0
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#define CONFIG_SERVERIP 192.168.0.1
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#define CONFIG_BOOTARGS \
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"console=ttyS0,115200 " \
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"root=/dev/nfs rw nfsroot=192.168.0.1:/opt/eldk/ppc_82xx " \
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"ip=192.168.0.2:192.168.0.1:192.168.0.1:255.255.255.0:" \
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"kvme080:eth0:none " \
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"mtdparts=phys_mapped_flash:12m(root),-(kernel)"
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#define CONFIG_BOOTCOMMAND \
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"tftp 800000 kvme080/uImage; " \
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"bootm 800000"
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#define CONFIG_LOADADDR 800000
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#define CONFIG_BOARD_EARLY_INIT_F
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#define CONFIG_BOARD_EARLY_INIT_R
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#define CONFIG_MISC_INIT_R
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#define CONFIG_LOADS_ECHO 1
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#undef CFG_LOADS_BAUD_CHANGE
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#undef CONFIG_WATCHDOG
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#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
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#define CONFIG_MAC_PARTITION
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#define CONFIG_DOS_PARTITION
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#define CONFIG_RTC_DS164x
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#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
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CFG_CMD_ASKENV | \
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CFG_CMD_CACHE | \
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CFG_CMD_DATE | \
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CFG_CMD_DHCP | \
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CFG_CMD_DIAG | \
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CFG_CMD_EEPROM | \
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CFG_CMD_ELF | \
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CFG_CMD_I2C | \
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CFG_CMD_JFFS2 | \
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CFG_CMD_NFS | \
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CFG_CMD_PCI | \
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CFG_CMD_PING | \
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CFG_CMD_SDRAM | \
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CFG_CMD_SNTP)
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#define CONFIG_NETCONSOLE
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#include <cmd_confdefs.h>
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#define CFG_LONGHELP
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#define CFG_PROMPT "=> "
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#define CFG_CBSIZE 256
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#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
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#define CFG_MAXARGS 16
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#define CFG_BARGSIZE CFG_CBSIZE
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#define CFG_MEMTEST_START 0x00400000
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#define CFG_MEMTEST_END 0x07C00000
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#define CFG_LOAD_ADDR 0x00100000
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#define CFG_HZ 1000
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#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
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#define CFG_INIT_RAM_ADDR 0x40000000
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#define CFG_INIT_RAM_END 0x1000
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#define CFG_GBL_DATA_SIZE 128
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#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
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#define CFG_SDRAM_BASE 0x00000000
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#define CFG_FLASH_BASE 0x7C000000
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#define CFG_EUMB_ADDR 0xFC000000
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#define CFG_NVRAM_BASE_ADDR 0xFF000000
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#define CFG_NS16550_COM1 0xFF080000
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#define CFG_NS16550_COM2 0xFF080010
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#define CFG_NS16550_COM3 0xFF080020
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#define CFG_NS16550_COM4 0xFF080030
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#define CFG_RESET_ADDRESS 0xFFF00100
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#define CFG_MAX_RAM_SIZE 0x20000000
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#define CFG_FLASH_SIZE (16 * 1024 * 1024)
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#define CFG_NVRAM_SIZE 0x7FFF8
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#define CONFIG_VERY_BIG_RAM
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#define CFG_MONITOR_LEN 0x00040000
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#define CFG_MONITOR_BASE TEXT_BASE
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#define CFG_MALLOC_LEN (512 << 10)
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#define CFG_BOOTMAPSZ (8 << 20)
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#define CFG_FLASH_CFI
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#define CFG_FLASH_CFI_DRIVER
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#define CFG_FLASH_USE_BUFFER_WRITE
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#define CFG_FLASH_PROTECTION
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#define CFG_FLASH_EMPTY_INFO
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#define CFG_FLASH_PROTECT_CLEAR
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#define CFG_MAX_FLASH_BANKS 1
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#define CFG_MAX_FLASH_SECT 256
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#define CFG_FLASH_ERASE_TOUT 120000
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#define CFG_FLASH_WRITE_TOUT 500
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#define CFG_JFFS2_FIRST_BANK 0
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#define CFG_JFFS2_NUM_BANKS 1
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#define CFG_ENV_IS_IN_NVRAM 1
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#define CONFIG_ENV_OVERWRITE 1
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#define CFG_NVRAM_ACCESS_ROUTINE
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#define CFG_ENV_ADDR CFG_NVRAM_BASE_ADDR
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#define CFG_ENV_SIZE 0x400
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#define CFG_ENV_OFFSET 0
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#define CFG_NS16550
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#define CFG_NS16550_SERIAL
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#define CFG_NS16550_REG_SIZE 1
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#define CFG_NS16550_CLK 14745600
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#define CONFIG_PCI
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#define CONFIG_PCI_PNP
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#define CONFIG_NET_MULTI
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#define CONFIG_EEPRO100
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#define CONFIG_EEPRO100_SROM_WRITE
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#define CFG_RX_ETH_BUFFER 8
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#define CONFIG_HARD_I2C 1
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#define CFG_I2C_SPEED 400000
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#define CFG_I2C_SLAVE 0x7F
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#define CFG_I2C_EEPROM_ADDR 0x57
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#define CFG_I2C_EEPROM_ADDR_LEN 1
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#define CFG_EEPROM_PAGE_WRITE_BITS 3
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#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
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#define CONFIG_SYS_CLK_FREQ 33333333
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#define CFG_CACHELINE_SIZE 32
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#if CONFIG_COMMANDS & CFG_CMD_KGDB
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# define CFG_CACHELINE_SHIFT 5
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#endif
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#define CFG_DLL_EXTEND 0x00
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#define CFG_PCI_HOLD_DEL 0x20
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#define CFG_ROMNAL 15
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#define CFG_ROMFAL 31
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#define CFG_REFINT 430
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#define CFG_DBUS_SIZE2 1
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#define CFG_BSTOPRE 121
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#define CFG_REFREC 8
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#define CFG_RDLAT 4
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#define CFG_PRETOACT 3
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#define CFG_ACTTOPRE 5
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#define CFG_ACTORW 3
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#define CFG_SDMODE_CAS_LAT 3
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#define CFG_SDMODE_WRAP 0
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#define CFG_REGISTERD_TYPE_BUFFER 1
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#define CFG_EXTROM 1
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#define CFG_REGDIMM 0
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#define CFG_BANK0_START 0x00000000
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#define CFG_BANK0_END (0x4000000 - 1)
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#define CFG_BANK0_ENABLE 1
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#define CFG_BANK1_START 0x04000000
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#define CFG_BANK1_END (0x8000000 - 1)
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#define CFG_BANK1_ENABLE 1
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#define CFG_BANK2_START 0x3ff00000
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#define CFG_BANK2_END 0x3fffffff
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#define CFG_BANK2_ENABLE 0
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#define CFG_BANK3_START 0x3ff00000
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#define CFG_BANK3_END 0x3fffffff
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#define CFG_BANK3_ENABLE 0
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#define CFG_BANK4_START 0x00000000
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#define CFG_BANK4_END 0x00000000
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#define CFG_BANK4_ENABLE 0
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#define CFG_BANK5_START 0x00000000
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#define CFG_BANK5_END 0x00000000
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#define CFG_BANK5_ENABLE 0
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#define CFG_BANK6_START 0x00000000
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#define CFG_BANK6_END 0x00000000
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#define CFG_BANK6_ENABLE 0
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#define CFG_BANK7_START 0x00000000
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#define CFG_BANK7_END 0x00000000
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#define CFG_BANK7_ENABLE 0
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#define CFG_BANK_ENABLE 0x03
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#define CFG_ODCR 0x75
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#define CFG_PGMAX 0x32
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#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
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#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
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#define CFG_IBAT1L (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
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#define CFG_IBAT1U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
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#define CFG_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
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#define CFG_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
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#define CFG_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
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#define CFG_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
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#define CFG_DBAT0L CFG_IBAT0L
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#define CFG_DBAT0U CFG_IBAT0U
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#define CFG_DBAT1L CFG_IBAT1L
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#define CFG_DBAT1U CFG_IBAT1U
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#define CFG_DBAT2L CFG_IBAT2L
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#define CFG_DBAT2U CFG_IBAT2U
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#define CFG_DBAT3L CFG_IBAT3L
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#define CFG_DBAT3U CFG_IBAT3U
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#define BOOTFLAG_COLD 0x01
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#define BOOTFLAG_WARM 0x02
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#endif /* __CONFIG_H */
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