mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-25 04:23:46 +00:00
f7ae49fc4f
Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
159 lines
3.7 KiB
C
159 lines
3.7 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2014-2016 Stefan Roese <sr@denx.de>
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*/
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#include <common.h>
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#include <dm.h>
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#include <debug_uart.h>
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#include <fdtdec.h>
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#include <hang.h>
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#include <init.h>
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#include <log.h>
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#include <spl.h>
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#include <asm/io.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/soc.h>
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static u32 get_boot_device(void)
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{
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u32 val;
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u32 boot_device;
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/*
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* First check, if UART boot-mode is active. This can only
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* be done, via the bootrom error register. Here the
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* MSB marks if the UART mode is active.
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*/
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val = readl(CONFIG_BOOTROM_ERR_REG);
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boot_device = (val & BOOTROM_ERR_MODE_MASK) >> BOOTROM_ERR_MODE_OFFS;
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debug("BOOTROM_REG=0x%08x boot_device=0x%x\n", val, boot_device);
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if (boot_device == BOOTROM_ERR_MODE_UART)
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return BOOT_DEVICE_UART;
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#ifdef CONFIG_ARMADA_38X
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/*
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* If the bootrom error code contains any other than zeros it's an
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* error condition and the bootROM has fallen back to UART boot
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*/
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boot_device = (val & BOOTROM_ERR_CODE_MASK) >> BOOTROM_ERR_CODE_OFFS;
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if (boot_device)
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return BOOT_DEVICE_UART;
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#endif
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/*
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* Now check the SAR register for the strapped boot-device
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*/
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val = readl(CONFIG_SAR_REG); /* SAR - Sample At Reset */
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boot_device = (val & BOOT_DEV_SEL_MASK) >> BOOT_DEV_SEL_OFFS;
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debug("SAR_REG=0x%08x boot_device=0x%x\n", val, boot_device);
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switch (boot_device) {
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#if defined(CONFIG_ARMADA_38X)
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case BOOT_FROM_NAND:
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return BOOT_DEVICE_NAND;
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#endif
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#ifdef CONFIG_SPL_MMC_SUPPORT
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case BOOT_FROM_MMC:
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case BOOT_FROM_MMC_ALT:
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return BOOT_DEVICE_MMC1;
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#endif
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case BOOT_FROM_UART:
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#ifdef BOOT_FROM_UART_ALT
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case BOOT_FROM_UART_ALT:
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#endif
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return BOOT_DEVICE_UART;
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#ifdef BOOT_FROM_SATA
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case BOOT_FROM_SATA:
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case BOOT_FROM_SATA_ALT:
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return BOOT_DEVICE_SATA;
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#endif
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case BOOT_FROM_SPI:
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default:
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return BOOT_DEVICE_SPI;
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};
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}
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u32 spl_boot_device(void)
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{
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return get_boot_device();
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}
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void board_init_f(ulong dummy)
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{
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int ret;
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/*
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* Pin muxing needs to be done before UART output, since
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* on A38x the UART pins need some re-muxing for output
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* to work.
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*/
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board_early_init_f();
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/* Example code showing how to enable the debug UART on MVEBU */
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#ifdef EARLY_UART
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/*
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* Debug UART can be used from here if required:
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*
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* debug_uart_init();
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* printch('a');
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* printhex8(0x1234);
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* printascii("string");
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*/
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#endif
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/*
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* Use special translation offset for SPL. This needs to be
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* configured *before* spl_init() is called as this function
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* calls dm_init() which calls the bind functions of the
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* device drivers. Here the base address needs to be configured
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* (translated) correctly.
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*/
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gd->translation_offset = 0xd0000000 - 0xf1000000;
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ret = spl_init();
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if (ret) {
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debug("spl_init() failed: %d\n", ret);
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hang();
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}
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preloader_console_init();
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timer_init();
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/* Armada 375 does not support SerDes and DDR3 init yet */
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#if !defined(CONFIG_ARMADA_375)
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/* First init the serdes PHY's */
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serdes_phy_config();
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/* Setup DDR */
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ddr3_init();
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#endif
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/* Initialize Auto Voltage Scaling */
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mv_avs_init();
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/* Update read timing control for PCIe */
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mv_rtc_config();
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/*
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* Return to the BootROM to continue the Marvell xmodem
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* UART boot protocol. As initiated by the kwboot tool.
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*
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* This can only be done by the BootROM and not by the
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* U-Boot SPL infrastructure, since the beginning of the
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* image is already read and interpreted by the BootROM.
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* SPL has no chance to receive this information. So we
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* need to return to the BootROM to enable this xmodem
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* UART download.
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*
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* If booting from NAND lets let the BootROM load the
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* rest of the bootloader.
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*/
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switch (get_boot_device()) {
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case BOOT_DEVICE_UART:
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#if defined(CONFIG_ARMADA_38X)
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case BOOT_DEVICE_NAND:
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#endif
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return_to_bootrom();
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}
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}
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