mirror of
https://github.com/AsahiLinux/u-boot
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1110e49e34
This imports the G12A & SM1 SoC and boards DT changes from the Linux
commit 9123e3a74ec7 ("Linux 5.9-rc1").
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Kevin Hilman <khilman@baylibre.com>
Tested-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
187 lines
3.6 KiB
Text
187 lines
3.6 KiB
Text
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2019 BayLibre, SAS
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* Author: Neil Armstrong <narmstrong@baylibre.com>
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*/
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/dts-v1/;
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#include "meson-sm1.dtsi"
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#include "meson-khadas-vim3.dtsi"
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#include <dt-bindings/sound/meson-g12a-tohdmitx.h>
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/ {
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compatible = "khadas,vim3l", "amlogic,sm1";
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model = "Khadas VIM3L";
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vddcpu: regulator-vddcpu {
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/*
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* Silergy SY8030DEC Regulator.
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*/
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compatible = "pwm-regulator";
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regulator-name = "VDDCPU";
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regulator-min-microvolt = <690000>;
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regulator-max-microvolt = <1050000>;
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vin-supply = <&vsys_3v3>;
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pwms = <&pwm_AO_cd 1 1250 0>;
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pwm-dutycycle-range = <100 0>;
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regulator-boot-on;
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regulator-always-on;
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};
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sound {
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compatible = "amlogic,axg-sound-card";
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model = "SM1-KHADAS-VIM3L";
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audio-aux-devs = <&tdmout_a>;
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audio-routing = "TDMOUT_A IN 0", "FRDDR_A OUT 0",
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"TDMOUT_A IN 1", "FRDDR_B OUT 0",
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"TDMOUT_A IN 2", "FRDDR_C OUT 0",
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"TDM_A Playback", "TDMOUT_A OUT";
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assigned-clocks = <&clkc CLKID_MPLL2>,
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<&clkc CLKID_MPLL0>,
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<&clkc CLKID_MPLL1>;
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assigned-clock-parents = <0>, <0>, <0>;
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assigned-clock-rates = <294912000>,
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<270950400>,
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<393216000>;
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status = "okay";
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dai-link-0 {
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sound-dai = <&frddr_a>;
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};
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dai-link-1 {
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sound-dai = <&frddr_b>;
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};
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dai-link-2 {
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sound-dai = <&frddr_c>;
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};
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/* 8ch hdmi interface */
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dai-link-3 {
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sound-dai = <&tdmif_a>;
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dai-format = "i2s";
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dai-tdm-slot-tx-mask-0 = <1 1>;
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dai-tdm-slot-tx-mask-1 = <1 1>;
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dai-tdm-slot-tx-mask-2 = <1 1>;
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dai-tdm-slot-tx-mask-3 = <1 1>;
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mclk-fs = <256>;
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codec {
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sound-dai = <&tohdmitx TOHDMITX_I2S_IN_A>;
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};
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};
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/* hdmi glue */
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dai-link-4 {
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sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>;
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codec {
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sound-dai = <&hdmi_tx>;
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};
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};
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};
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};
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&arb {
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status = "okay";
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};
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&clkc_audio {
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status = "okay";
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};
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&cpu0 {
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cpu-supply = <&vddcpu>;
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operating-points-v2 = <&cpu_opp_table>;
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clocks = <&clkc CLKID_CPU_CLK>;
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clock-latency = <50000>;
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};
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&cpu1 {
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cpu-supply = <&vddcpu>;
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operating-points-v2 = <&cpu_opp_table>;
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clocks = <&clkc CLKID_CPU1_CLK>;
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clock-latency = <50000>;
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};
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&cpu2 {
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cpu-supply = <&vddcpu>;
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operating-points-v2 = <&cpu_opp_table>;
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clocks = <&clkc CLKID_CPU2_CLK>;
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clock-latency = <50000>;
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};
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&cpu3 {
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cpu-supply = <&vddcpu>;
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operating-points-v2 = <&cpu_opp_table>;
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clocks = <&clkc CLKID_CPU3_CLK>;
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clock-latency = <50000>;
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};
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&frddr_a {
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status = "okay";
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};
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&frddr_b {
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status = "okay";
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};
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&frddr_c {
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status = "okay";
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};
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&pwm_AO_cd {
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pinctrl-0 = <&pwm_ao_d_e_pins>;
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pinctrl-names = "default";
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clocks = <&xtal>;
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clock-names = "clkin1";
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status = "okay";
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};
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/*
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* The VIM3 on-board MCU can mux the PCIe/USB3.0 shared differential
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* lines using a FUSB340TMX USB 3.1 SuperSpeed Data Switch between
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* an USB3.0 Type A connector and a M.2 Key M slot.
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* The PHY driving these differential lines is shared between
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* the USB3.0 controller and the PCIe Controller, thus only
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* a single controller can use it.
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* If the MCU is configured to mux the PCIe/USB3.0 differential lines
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* to the M.2 Key M slot, uncomment the following block to disable
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* USB3.0 from the USB Complex and enable the PCIe controller.
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* The End User is not expected to uncomment the following except for
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* testing purposes, but instead rely on the firmware/bootloader to
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* update these nodes accordingly if PCIe mode is selected by the MCU.
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*/
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/*
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&pcie {
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status = "okay";
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};
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&sd_emmc_a {
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sd-uhs-sdr50;
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};
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&usb {
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phys = <&usb2_phy0>, <&usb2_phy1>;
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phy-names = "usb2-phy0", "usb2-phy1";
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};
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*/
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&tdmif_a {
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status = "okay";
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};
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&tdmout_a {
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status = "okay";
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};
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&tohdmitx {
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status = "okay";
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};
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