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https://github.com/AsahiLinux/u-boot
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2d6bf754ce
Lower case should be used for function names. Update this driver and its callers accordingly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
313 lines
8.7 KiB
C
313 lines
8.7 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* SoC-specific lowlevel code for DA850
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*
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* Copyright (C) 2011
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* Heiko Schocher, DENX Software Engineering, hs@denx.de.
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*/
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#include <common.h>
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#include <init.h>
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#include <nand.h>
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#include <ns16550.h>
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#include <post.h>
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#include <asm/arch/da850_lowlevel.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/davinci_misc.h>
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#include <asm/arch/ddr2_defs.h>
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#include <asm/ti-common/davinci_nand.h>
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#include <asm/arch/pll_defs.h>
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void davinci_enable_uart0(void)
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{
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lpsc_on(DAVINCI_LPSC_UART0);
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/* Bringup UART0 out of reset */
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REG(UART0_PWREMU_MGMT) = 0x00006001;
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}
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#if defined(CONFIG_SYS_DA850_PLL_INIT)
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static void da850_waitloop(unsigned long loopcnt)
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{
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unsigned long i;
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for (i = 0; i < loopcnt; i++)
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asm(" NOP");
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}
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static int da850_pll_init(struct davinci_pllc_regs *reg, unsigned long pllmult)
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{
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if (reg == davinci_pllc0_regs)
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/* Unlock PLL registers. */
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clrbits_le32(&davinci_syscfg_regs->cfgchip0, PLL_MASTER_LOCK);
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/*
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* Set PLLENSRC '0',bit 5, PLL Enable(PLLEN) selection is controlled
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* through MMR
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*/
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clrbits_le32(®->pllctl, PLLCTL_PLLENSRC);
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/* PLLCTL.EXTCLKSRC bit 9 should be left at 0 for Freon */
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clrbits_le32(®->pllctl, PLLCTL_EXTCLKSRC);
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/* Set PLLEN=0 => PLL BYPASS MODE */
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clrbits_le32(®->pllctl, PLLCTL_PLLEN);
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da850_waitloop(150);
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if (reg == davinci_pllc0_regs) {
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/*
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* Select the Clock Mode bit 8 as External Clock or On Chip
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* Oscilator
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*/
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dv_maskbits(®->pllctl, ~PLLCTL_RES_9);
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setbits_le32(®->pllctl,
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(CONFIG_SYS_DV_CLKMODE << PLLCTL_CLOCK_MODE_SHIFT));
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}
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/* Clear PLLRST bit to reset the PLL */
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clrbits_le32(®->pllctl, PLLCTL_PLLRST);
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/* Disable the PLL output */
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setbits_le32(®->pllctl, PLLCTL_PLLDIS);
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/* PLL initialization sequence */
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/*
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* Power up the PLL- PWRDN bit set to 0 to bring the PLL out of
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* power down bit
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*/
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clrbits_le32(®->pllctl, PLLCTL_PLLPWRDN);
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/* Enable the PLL from Disable Mode PLLDIS bit to 0 */
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clrbits_le32(®->pllctl, PLLCTL_PLLDIS);
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#if defined(CONFIG_SYS_DA850_PLL0_PREDIV)
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/* program the prediv */
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if (reg == davinci_pllc0_regs && CONFIG_SYS_DA850_PLL0_PREDIV)
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writel((PLL_DIVEN | CONFIG_SYS_DA850_PLL0_PREDIV),
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®->prediv);
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#endif
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/* Program the required multiplier value in PLLM */
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writel(pllmult, ®->pllm);
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/* program the postdiv */
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if (reg == davinci_pllc0_regs)
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writel((PLL_POSTDEN | CONFIG_SYS_DA850_PLL0_POSTDIV),
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®->postdiv);
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else
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writel((PLL_POSTDEN | CONFIG_SYS_DA850_PLL1_POSTDIV),
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®->postdiv);
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/*
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* Check for the GOSTAT bit in PLLSTAT to clear to 0 to indicate that
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* no GO operation is currently in progress
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*/
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while ((readl(®->pllstat) & PLLCMD_GOSTAT) == PLLCMD_GOSTAT)
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;
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if (reg == davinci_pllc0_regs) {
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writel(CONFIG_SYS_DA850_PLL0_PLLDIV1, ®->plldiv1);
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writel(CONFIG_SYS_DA850_PLL0_PLLDIV2, ®->plldiv2);
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writel(CONFIG_SYS_DA850_PLL0_PLLDIV3, ®->plldiv3);
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writel(CONFIG_SYS_DA850_PLL0_PLLDIV4, ®->plldiv4);
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writel(CONFIG_SYS_DA850_PLL0_PLLDIV5, ®->plldiv5);
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writel(CONFIG_SYS_DA850_PLL0_PLLDIV6, ®->plldiv6);
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writel(CONFIG_SYS_DA850_PLL0_PLLDIV7, ®->plldiv7);
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} else {
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writel(CONFIG_SYS_DA850_PLL1_PLLDIV1, ®->plldiv1);
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writel(CONFIG_SYS_DA850_PLL1_PLLDIV2, ®->plldiv2);
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writel(CONFIG_SYS_DA850_PLL1_PLLDIV3, ®->plldiv3);
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}
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/*
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* Set the GOSET bit in PLLCMD to 1 to initiate a new divider
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* transition.
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*/
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setbits_le32(®->pllcmd, PLLCMD_GOSTAT);
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/*
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* Wait for the GOSTAT bit in PLLSTAT to clear to 0
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* (completion of phase alignment).
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*/
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while ((readl(®->pllstat) & PLLCMD_GOSTAT) == PLLCMD_GOSTAT)
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;
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/* Wait for PLL to reset properly. See PLL spec for PLL reset time */
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da850_waitloop(200);
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/* Set the PLLRST bit in PLLCTL to 1 to bring the PLL out of reset */
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setbits_le32(®->pllctl, PLLCTL_PLLRST);
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/* Wait for PLL to lock. See PLL spec for PLL lock time */
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da850_waitloop(2400);
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/*
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* Set the PLLEN bit in PLLCTL to 1 to remove the PLL from bypass
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* mode
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*/
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setbits_le32(®->pllctl, PLLCTL_PLLEN);
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/*
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* clear EMIFA and EMIFB clock source settings, let them
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* run off SYSCLK
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*/
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if (reg == davinci_pllc0_regs)
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dv_maskbits(&davinci_syscfg_regs->cfgchip3,
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~(PLL_SCSCFG3_DIV45PENA | PLL_SCSCFG3_EMA_CLKSRC));
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return 0;
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}
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#endif /* CONFIG_SYS_DA850_PLL_INIT */
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#if defined(CONFIG_SYS_DA850_DDR_INIT)
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static int da850_ddr_setup(void)
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{
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unsigned long tmp;
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/* Enable the Clock to DDR2/mDDR */
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lpsc_on(DAVINCI_LPSC_DDR_EMIF);
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tmp = readl(&davinci_syscfg1_regs->vtpio_ctl);
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if ((tmp & VTP_POWERDWN) == VTP_POWERDWN) {
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/* Begin VTP Calibration */
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clrbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_POWERDWN);
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clrbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_LOCK);
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setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_CLKRZ);
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clrbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_CLKRZ);
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setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_CLKRZ);
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/* Polling READY bit to see when VTP calibration is done */
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tmp = readl(&davinci_syscfg1_regs->vtpio_ctl);
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while ((tmp & VTP_READY) != VTP_READY)
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tmp = readl(&davinci_syscfg1_regs->vtpio_ctl);
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setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_LOCK);
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setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_POWERDWN);
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}
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setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_IOPWRDWN);
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writel(CONFIG_SYS_DA850_DDR2_DDRPHYCR, &dv_ddr2_regs_ctrl->ddrphycr);
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if (CONFIG_SYS_DA850_DDR2_SDBCR & (1 << DV_DDR_SDCR_DDR2EN_SHIFT)) {
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/* DDR2 */
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clrbits_le32(&davinci_syscfg1_regs->ddr_slew,
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(1 << DDR_SLEW_DDR_PDENA_BIT) |
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(1 << DDR_SLEW_CMOSEN_BIT));
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} else {
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/* MOBILE DDR */
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setbits_le32(&davinci_syscfg1_regs->ddr_slew,
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(1 << DDR_SLEW_DDR_PDENA_BIT) |
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(1 << DDR_SLEW_CMOSEN_BIT));
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}
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/*
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* SDRAM Configuration Register (SDCR):
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* First set the BOOTUNLOCK bit to make configuration bits
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* writeable.
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*/
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setbits_le32(&dv_ddr2_regs_ctrl->sdbcr, DV_DDR_BOOTUNLOCK);
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/*
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* Write the new value of these bits and clear BOOTUNLOCK.
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* At the same time, set the TIMUNLOCK bit to allow changing
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* the timing registers
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*/
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tmp = CONFIG_SYS_DA850_DDR2_SDBCR;
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tmp &= ~DV_DDR_BOOTUNLOCK;
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tmp |= DV_DDR_TIMUNLOCK;
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writel(tmp, &dv_ddr2_regs_ctrl->sdbcr);
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/* write memory configuration and timing */
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if (!(CONFIG_SYS_DA850_DDR2_SDBCR & (1 << DV_DDR_SDCR_DDR2EN_SHIFT))) {
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/* MOBILE DDR only*/
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writel(CONFIG_SYS_DA850_DDR2_SDBCR2,
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&dv_ddr2_regs_ctrl->sdbcr2);
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}
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writel(CONFIG_SYS_DA850_DDR2_SDTIMR, &dv_ddr2_regs_ctrl->sdtimr);
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writel(CONFIG_SYS_DA850_DDR2_SDTIMR2, &dv_ddr2_regs_ctrl->sdtimr2);
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/* clear the TIMUNLOCK bit and write the value of the CL field */
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tmp &= ~DV_DDR_TIMUNLOCK;
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writel(tmp, &dv_ddr2_regs_ctrl->sdbcr);
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/*
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* LPMODEN and MCLKSTOPEN must be set!
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* Without this bits set, PSC don;t switch states !!
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*/
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writel(CONFIG_SYS_DA850_DDR2_SDRCR |
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(1 << DV_DDR_SRCR_LPMODEN_SHIFT) |
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(1 << DV_DDR_SRCR_MCLKSTOPEN_SHIFT),
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&dv_ddr2_regs_ctrl->sdrcr);
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/* SyncReset the Clock to EMIF3A SDRAM */
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lpsc_syncreset(DAVINCI_LPSC_DDR_EMIF);
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/* Enable the Clock to EMIF3A SDRAM */
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lpsc_on(DAVINCI_LPSC_DDR_EMIF);
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/* disable self refresh */
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clrbits_le32(&dv_ddr2_regs_ctrl->sdrcr,
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DV_DDR_SDRCR_LPMODEN | DV_DDR_SDRCR_MCLKSTOPEN);
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writel(CONFIG_SYS_DA850_DDR2_PBBPR, &dv_ddr2_regs_ctrl->pbbpr);
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return 0;
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}
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#endif /* CONFIG_SYS_DA850_DDR_INIT */
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__attribute__((weak))
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void board_gpio_init(void)
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{
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return;
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}
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int arch_cpu_init(void)
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{
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/* Unlock kick registers */
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writel(DV_SYSCFG_KICK0_UNLOCK, &davinci_syscfg_regs->kick0);
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writel(DV_SYSCFG_KICK1_UNLOCK, &davinci_syscfg_regs->kick1);
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dv_maskbits(&davinci_syscfg_regs->suspsrc,
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CONFIG_SYS_DA850_SYSCFG_SUSPSRC);
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/* configure pinmux settings */
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if (davinci_configure_pin_mux_items(pinmuxes, pinmuxes_size))
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return 1;
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#if defined(CONFIG_SYS_DA850_PLL_INIT)
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/* PLL setup */
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da850_pll_init(davinci_pllc0_regs, CONFIG_SYS_DA850_PLL0_PLLM);
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da850_pll_init(davinci_pllc1_regs, CONFIG_SYS_DA850_PLL1_PLLM);
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#endif
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/* setup CSn config */
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#if defined(CONFIG_SYS_DA850_CS2CFG)
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writel(CONFIG_SYS_DA850_CS2CFG, &davinci_emif_regs->ab1cr);
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#endif
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#if defined(CONFIG_SYS_DA850_CS3CFG)
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writel(CONFIG_SYS_DA850_CS3CFG, &davinci_emif_regs->ab2cr);
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#endif
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da8xx_configure_lpsc_items(lpsc, lpsc_size);
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/* GPIO setup */
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board_gpio_init();
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#if !CONFIG_IS_ENABLED(DM_SERIAL)
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ns16550_init((struct ns16550 *)(CONFIG_SYS_NS16550_COM1),
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CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
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#endif
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/*
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* Fix Power and Emulation Management Register
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* see sprufw3a.pdf page 37 Table 24
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*/
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writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST |
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DAVINCI_UART_PWREMU_MGMT_UTRST),
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#if (CONFIG_SYS_NS16550_COM1 == DAVINCI_UART0_BASE)
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&davinci_uart0_ctrl_regs->pwremu_mgmt);
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#else
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&davinci_uart2_ctrl_regs->pwremu_mgmt);
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#endif
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#if defined(CONFIG_SYS_DA850_DDR_INIT)
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da850_ddr_setup();
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#endif
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return 0;
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}
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