mirror of
https://github.com/AsahiLinux/u-boot
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cccea18813
The number of image array entries global variable is required to support EFI capsule update. This information is exposed as a num_image_type_guids variable, but this information should be included in the efi_capsule_update_info structure. This commit adds the num_images member in the efi_capsule_update_info structure. All board files supporting EFI capsule update are updated. Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org> Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
208 lines
4.3 KiB
C
208 lines
4.3 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2019 NXP
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* Copyright 2022 Linaro
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*/
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#include <common.h>
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#include <dwc3-uboot.h>
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#include <efi.h>
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#include <efi_loader.h>
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#include <errno.h>
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#include <miiphy.h>
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#include <netdev.h>
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#include <spl.h>
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#include <usb.h>
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#include <asm/io.h>
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#include <asm/mach-imx/iomux-v3.h>
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#include <asm-generic/gpio.h>
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#include <asm/arch/imx8mp_pins.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/mach-imx/gpio.h>
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#include <asm/mach-imx/mxc_i2c.h>
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#include <asm/arch/clock.h>
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#include <asm/mach-imx/dma.h>
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#include <linux/delay.h>
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#include <linux/kernel.h>
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#include <power/pmic.h>
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DECLARE_GLOBAL_DATA_PTR;
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#ifdef CONFIG_NAND_MXS
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static void setup_gpmi_nand(void)
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{
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init_nand_clk();
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}
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#endif
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#if IS_ENABLED(CONFIG_EFI_HAVE_CAPSULE_SUPPORT)
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struct efi_fw_image fw_images[] = {
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#if defined(CONFIG_TARGET_IMX8MP_RSB3720A1_4G)
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{
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.image_type_id = IMX8MP_RSB3720A1_4G_FIT_IMAGE_GUID,
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.fw_name = u"IMX8MP-RSB3720-FIT",
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.image_index = 1,
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},
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#elif defined(CONFIG_TARGET_IMX8MP_RSB3720A1_6G)
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{
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.image_type_id = IMX8MP_RSB3720A1_6G_FIT_IMAGE_GUID,
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.fw_name = u"IMX8MP-RSB3720-FIT",
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.image_index = 1,
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},
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#endif
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};
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struct efi_capsule_update_info update_info = {
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.dfu_string = "mmc 2=flash-bin raw 0 0x1B00 mmcpart 1",
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.num_images = ARRAY_SIZE(fw_images),
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.images = fw_images,
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};
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#endif /* EFI_HAVE_CAPSULE_SUPPORT */
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int board_early_init_f(void)
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{
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init_uart_clk(2);
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return 0;
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}
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#ifdef CONFIG_OF_BOARD_SETUP
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int ft_board_setup(void *blob, struct bd_info *bd)
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{
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return 0;
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}
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#endif
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#ifdef CONFIG_FEC_MXC
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#define FEC_RST_PAD IMX_GPIO_NR(4, 2)
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static const iomux_v3_cfg_t fec1_rst_pads[] = {
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MX8MP_PAD_SAI1_RXD0__GPIO4_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL),
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};
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static void setup_iomux_fec(void)
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{
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imx_iomux_v3_setup_multiple_pads(fec1_rst_pads,
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ARRAY_SIZE(fec1_rst_pads));
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gpio_request(FEC_RST_PAD, "fec1_rst");
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gpio_direction_output(FEC_RST_PAD, 0);
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mdelay(15);
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gpio_direction_output(FEC_RST_PAD, 1);
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mdelay(100);
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}
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static int setup_fec(void)
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{
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struct iomuxc_gpr_base_regs *gpr =
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(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
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setup_iomux_fec();
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/* Enable RGMII TX clk output */
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setbits_le32(&gpr->gpr[1], BIT(22));
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return 0;
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}
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#endif /* CONFIG_FEC_MXC */
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#ifdef CONFIG_DWC_ETH_QOS
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#define EQOS_RST_PAD IMX_GPIO_NR(4, 22)
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static const iomux_v3_cfg_t eqos_rst_pads[] = {
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MX8MP_PAD_SAI2_RXC__GPIO4_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL),
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};
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static void setup_eqos(void)
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{
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imx_iomux_v3_setup_multiple_pads(eqos_rst_pads,
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ARRAY_SIZE(eqos_rst_pads));
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gpio_request(EQOS_RST_PAD, "eqos_rst");
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gpio_direction_output(EQOS_RST_PAD, 0);
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mdelay(15);
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gpio_direction_output(EQOS_RST_PAD, 1);
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mdelay(100);
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}
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#endif /* CONFIG_DWC_ETH_QOS */
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int board_phy_config(struct phy_device *phydev)
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{
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if (IS_ENABLED(CONFIG_FEC_MXC) || IS_ENABLED(CONFIG_DWC_ETH_QOS)) {
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/* enable rgmii rxc skew and phy mode select to RGMII copper */
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phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
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phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
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phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x00);
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phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x82ee);
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phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
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phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
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if (phydev->drv->config)
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phydev->drv->config(phydev);
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}
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return 0;
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}
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#define DISPMIX 13
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#define MIPI 15
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#define WDOG_TRIG IMX_GPIO_NR(4, 20)
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static iomux_v3_cfg_t wdt_trig[] = {
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MX8MP_PAD_SAI1_MCLK__GPIO4_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL),
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};
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static void setup_iomux_wdt(void)
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{
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imx_iomux_v3_setup_multiple_pads(wdt_trig, ARRAY_SIZE(wdt_trig));
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gpio_request(WDOG_TRIG, "wdt_trig");
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gpio_direction_output(WDOG_TRIG, 1);
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}
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int board_init(void)
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{
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#ifdef CONFIG_FEC_MXC
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setup_fec();
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#endif
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#ifdef CONFIG_DWC_ETH_QOS
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/* clock, pin, gpr */
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setup_eqos();
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#endif
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#ifdef CONFIG_NAND_MXS
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setup_gpmi_nand();
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#endif
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setup_iomux_wdt();
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return 0;
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}
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int board_late_init(void)
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{
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if (IS_ENABLED(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG)) {
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env_set("board_name", "RSB3720A1");
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env_set("board_rev", "iMX8MP");
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}
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return 0;
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}
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#ifdef CONFIG_SPL_MMC
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#define UBOOT_RAW_SECTOR_OFFSET 0x40
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unsigned long spl_mmc_get_uboot_raw_sector(struct mmc *mmc,
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unsigned long raw_sector)
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{
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u32 boot_dev = spl_boot_device();
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switch (boot_dev) {
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case BOOT_DEVICE_MMC2:
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return CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR - UBOOT_RAW_SECTOR_OFFSET;
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default:
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return CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR;
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}
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}
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#endif /* CONFIG_SPL_MMC */
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