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3e01ed00da
The definitions inside emif_defs.h concern davinci nand driver and should be in it's header. So create header file for davinci nand driver and move definitions from emif_defs.h and nand_defs.h to it. Acked-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com> [trini: Fixup more davinci breakage] Signed-off-by: Tom Rini <trini@ti.com>
134 lines
2.9 KiB
C
134 lines
2.9 KiB
C
/*
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* TNETV107X-EVM: Board initialization
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <miiphy.h>
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#include <linux/mtd/nand.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/clock.h>
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#include <asm/io.h>
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#include <asm/mach-types.h>
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#include <asm/ti-common/davinci_nand.h>
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#include <asm/arch/mux.h>
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DECLARE_GLOBAL_DATA_PTR;
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static struct async_emif_config async_emif_config[ASYNC_EMIF_NUM_CS] = {
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{ /* CS0 */
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.mode = ASYNC_EMIF_MODE_NAND,
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.wr_setup = 5,
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.wr_strobe = 5,
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.wr_hold = 2,
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.rd_setup = 5,
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.rd_strobe = 5,
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.rd_hold = 2,
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.turn_around = 5,
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.width = ASYNC_EMIF_8,
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},
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{ /* CS1 */
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.mode = ASYNC_EMIF_MODE_NOR,
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.wr_setup = 2,
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.wr_strobe = 27,
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.wr_hold = 4,
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.rd_setup = 2,
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.rd_strobe = 27,
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.rd_hold = 4,
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.turn_around = 2,
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.width = ASYNC_EMIF_PRESERVE,
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},
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{ /* CS2 */
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.mode = ASYNC_EMIF_MODE_NOR,
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.wr_setup = 2,
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.wr_strobe = 27,
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.wr_hold = 4,
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.rd_setup = 2,
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.rd_strobe = 27,
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.rd_hold = 4,
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.turn_around = 2,
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.width = ASYNC_EMIF_PRESERVE,
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},
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{ /* CS3 */
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.mode = ASYNC_EMIF_MODE_NOR,
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.wr_setup = 1,
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.wr_strobe = 90,
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.wr_hold = 3,
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.rd_setup = 1,
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.rd_strobe = 26,
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.rd_hold = 3,
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.turn_around = 1,
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.width = ASYNC_EMIF_8,
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},
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};
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static struct pll_init_data pll_config[] = {
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{
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.pll = ETH_PLL,
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.internal_osc = 1,
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.pll_freq = 500000000,
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.div_freq = {
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5000000, 50000000, 125000000, 250000000, 25000000,
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},
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},
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};
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static const short sdio1_pins[] = {
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TNETV107X_PIN_SDIO1_CLK_1, TNETV107X_PIN_SDIO1_CMD_1,
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TNETV107X_PIN_SDIO1_DATA0_1, TNETV107X_PIN_SDIO1_DATA1_1,
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TNETV107X_PIN_SDIO1_DATA2_1, TNETV107X_PIN_SDIO1_DATA3_1,
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-1
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};
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static const short uart1_pins[] = {
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TNETV107X_PIN_UART1_RD, TNETV107X_PIN_UART1_TD, -1
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};
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static const short ssp_pins[] = {
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TNETV107X_PIN_SSP0_0, TNETV107X_PIN_SSP0_1, TNETV107X_PIN_SSP0_2,
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TNETV107X_PIN_SSP1_0, TNETV107X_PIN_SSP1_1, TNETV107X_PIN_SSP1_2,
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TNETV107X_PIN_SSP1_3, -1
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};
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int board_init(void)
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{
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#ifndef CONFIG_USE_IRQ
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__raw_writel(0, INTC_GLB_EN); /* Global disable */
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__raw_writel(0, INTC_HINT_EN); /* Disable host ints */
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__raw_writel(0, INTC_EN_CLR0 + 0); /* Clear enable */
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__raw_writel(0, INTC_EN_CLR0 + 4); /* Clear enable */
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__raw_writel(0, INTC_EN_CLR0 + 8); /* Clear enable */
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#endif
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gd->bd->bi_arch_number = MACH_TYPE_TNETV107X;
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gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
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init_plls(ARRAY_SIZE(pll_config), pll_config);
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init_async_emif(ARRAY_SIZE(async_emif_config), async_emif_config);
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mux_select_pin(TNETV107X_PIN_ASR_CS3);
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mux_select_pins(sdio1_pins);
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mux_select_pins(uart1_pins);
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mux_select_pins(ssp_pins);
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return 0;
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}
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int dram_init(void)
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{
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gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
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gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
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return 0;
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}
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#ifdef CONFIG_NAND_DAVINCI
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int board_nand_init(struct nand_chip *nand)
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{
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davinci_nand_init(nand);
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return 0;
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}
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#endif
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