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5a5bba053d
Broadcom bnxt L2 driver support. Used by the Broadcom iproc platforms. Signed-off-by: Bharat Gooty <bharat.gooty@broadcom.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com> Signed-off-by: Roman Bacik <roman.bacik@broadcom.com>
390 lines
15 KiB
C
390 lines
15 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright 2019-2021 Broadcom.
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*/
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#ifndef _BNXT_H_
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#define _BNXT_H_
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#include <pci.h>
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#include <linux/if_ether.h>
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#include "bnxt_hsi.h"
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union dma_addr64_t {
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dma_addr_t addr;
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u64 as_u64;
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};
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#define DRIVER_VERSION_MAJOR 1
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#define DRIVER_VERSION_MINOR 0
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#define DRIVER_VERSION_UPDATE 0
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/* Broadcom ethernet driver defines. */
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#define FLAG_SET(f, b) ((f) |= (b))
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#define FLAG_TEST(f, b) ((f) & (b))
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#define FLAG_RESET(f, b) ((f) &= ~(b))
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#define BNXT_FLAG_HWRM_SHORT_CMD_SUPP BIT(0)
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#define BNXT_FLAG_HWRM_SHORT_CMD_REQ BIT(1)
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#define BNXT_FLAG_RESOURCE_QCAPS_SUPPORT BIT(2)
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#define BNXT_FLAG_MULTI_HOST BIT(3)
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#define BNXT_FLAG_NPAR_MODE BIT(4)
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/*******************************************************************************
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* Status codes.
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******************************************************************************/
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#define STATUS_SUCCESS 0
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#define STATUS_FAILURE 1
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#define STATUS_LINK_ACTIVE 4
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#define STATUS_LINK_DOWN 5
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#define STATUS_TIMEOUT 0xffff
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/*******************************************************************************
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* Receive filter masks.
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******************************************************************************/
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#define RX_MASK_ACCEPT_NONE 0x0000
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#define RX_MASK_ACCEPT_MULTICAST 0x0002
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#define RX_MASK_ACCEPT_ALL_MULTICAST 0x0004
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#define RX_MASK_ACCEPT_BROADCAST 0x0008
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#define RX_MASK_PROMISCUOUS_MODE 0x10000
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/*******************************************************************************
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* media speed.
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******************************************************************************/
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#define MEDIUM_SPEED_AUTONEG 0x0000L
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#define MEDIUM_SPEED_1000MBPS 0x0300L
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#define MEDIUM_SPEED_2500MBPS 0x0400L
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#define MEDIUM_SPEED_10GBPS 0x0600L
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#define MEDIUM_SPEED_25GBPS 0x0800L
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#define MEDIUM_SPEED_40GBPS 0x0900L
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#define MEDIUM_SPEED_50GBPS 0x0a00L
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#define MEDIUM_SPEED_100GBPS 0x0b00L
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#define MEDIUM_SPEED_200GBPS 0x0c00L
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#define MEDIUM_SPEED_MASK 0xff00L
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#define GET_MEDIUM_SPEED(m) ((m) & MEDIUM_SPEED_MASK)
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#define SET_MEDIUM_SPEED(bp, s) (((bp)->medium & ~MEDIUM_SPEED_MASK) | (s))
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#define MEDIUM_UNKNOWN_DUPLEX 0x00000L
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#define MEDIUM_FULL_DUPLEX 0x00000L
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#define MEDIUM_HALF_DUPLEX 0x10000L
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#define GET_MEDIUM_DUPLEX(m) ((m) & MEDIUM_HALF_DUPLEX)
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#define SET_MEDIUM_DUPLEX(bp, d) (((bp)->medium & ~MEDIUM_HALF_DUPLEX) | (d))
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#define MEDIUM_SELECTIVE_AUTONEG 0x01000000L
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#define GET_MEDIUM_AUTONEG_MODE(m) ((m) & 0xff000000L)
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#define GRC_COM_CHAN_BASE 0
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#define GRC_COM_CHAN_TRIG 0x100
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#define HWRM_CMD_DEFAULT_TIMEOUT 500 /* in Miliseconds */
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#define HWRM_CMD_POLL_WAIT_TIME 100 /* In MicroeSconds */
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#define HWRM_CMD_DEFAULT_MULTIPLAYER(a) ((a) * 10)
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#define HWRM_CMD_FLASH_MULTIPLAYER(a) ((a) * 100)
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#define HWRM_CMD_FLASH_ERASE_MULTIPLAYER(a) ((a) * 1000)
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#define MAX_ETHERNET_PACKET_BUFFER_SIZE 1536
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#define DEFAULT_NUMBER_OF_CMPL_RINGS 0x01
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#define DEFAULT_NUMBER_OF_TX_RINGS 0x01
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#define DEFAULT_NUMBER_OF_RX_RINGS 0x01
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#define DEFAULT_NUMBER_OF_RING_GRPS 0x01
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#define DEFAULT_NUMBER_OF_STAT_CTXS 0x01
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#define NUM_RX_BUFFERS 512
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#define MAX_RX_DESC_CNT 1024
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#define MAX_TX_DESC_CNT 512
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#define MAX_CQ_DESC_CNT 2048
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#define TX_RING_DMA_BUFFER_SIZE (MAX_TX_DESC_CNT * sizeof(struct tx_bd_short))
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#define RX_RING_DMA_BUFFER_SIZE \
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(MAX_RX_DESC_CNT * sizeof(struct rx_prod_pkt_bd))
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#define CQ_RING_DMA_BUFFER_SIZE (MAX_CQ_DESC_CNT * sizeof(struct cmpl_base))
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#define BNXT_DMA_ALIGNMENT 256 //64
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#define REQ_BUFFER_SIZE 1024
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#define RESP_BUFFER_SIZE 1024
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#define DMA_BUFFER_SIZE 1024
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#define LM_PAGE_BITS 8
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#define BNXT_RX_STD_DMA_SZ 1536
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#define NEXT_IDX(N, S) (((N) + 1) & ((S) - 1))
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#define BD_NOW(bd, entry, len) (&((u8 *)(bd))[(entry) * (len)])
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#define BNXT_CQ_INTR_MODE() RING_ALLOC_REQ_INT_MODE_POLL
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#define BNXT_INTR_MODE() RING_ALLOC_REQ_INT_MODE_POLL
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/* Set default link timeout period to 500 millseconds */
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#define LINK_DEFAULT_TIMEOUT 500
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#define RX_MASK \
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(RX_MASK_ACCEPT_BROADCAST | \
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RX_MASK_ACCEPT_ALL_MULTICAST | \
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RX_MASK_ACCEPT_MULTICAST)
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#define TX_RING_QID ((u16)bp->port_idx * 10)
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#define RX_RING_QID 0
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#define LM_PAGE_SIZE LM_PAGE_BITS
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#define virt_to_bus(a) ((dma_addr_t)(a))
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#define REQ_BUF_SIZE_ALIGNED ALIGN(REQ_BUFFER_SIZE, BNXT_DMA_ALIGNMENT)
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#define RESP_BUF_SIZE_ALIGNED ALIGN(RESP_BUFFER_SIZE, BNXT_DMA_ALIGNMENT)
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#define DMA_BUF_SIZE_ALIGNED ALIGN(DMA_BUFFER_SIZE, BNXT_DMA_ALIGNMENT)
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#define RX_STD_DMA_ALIGNED ALIGN(BNXT_RX_STD_DMA_SZ, BNXT_DMA_ALIGNMENT)
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#define PCI_COMMAND_INTX_DISABLE 0x0400 /* Interrupt disable */
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#define TX_AVAIL(r) ((r) - 1)
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#define NO_MORE_CQ_BD_TO_SERVICE 1
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#define SERVICE_NEXT_CQ_BD 0
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#define PHY_STATUS 0x0001
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#define PHY_SPEED 0x0002
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#define DETECT_MEDIA 0x0004
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#define SUPPORT_SPEEDS 0x0008
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#define str_1 "1"
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#define str_2 "2"
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#define str_2_5 "2.5"
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#define str_10 "10"
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#define str_20 "20"
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#define str_25 "25"
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#define str_40 "40"
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#define str_50 "50"
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#define str_100 "100"
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#define str_gbps "Gbps"
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#define str_mbps "Mbps"
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#define str_unknown "Unknown"
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/* Broadcom ethernet driver nvm defines. */
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/* nvm cfg 1 - MAC settings */
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#define FUNC_MAC_ADDR_NUM 1
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/* nvm cfg 203 - u32 link_settings */
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#define LINK_SPEED_DRV_NUM 203
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#define LINK_SPEED_DRV_MASK 0x0000000F
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#define LINK_SPEED_DRV_SHIFT 0
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#define LINK_SPEED_DRV_AUTONEG 0x0
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#define LINK_SPEED_DRV_1G 0x1
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#define LINK_SPEED_DRV_10G 0x2
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#define LINK_SPEED_DRV_25G 0x3
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#define LINK_SPEED_DRV_40G 0x4
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#define LINK_SPEED_DRV_50G 0x5
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#define LINK_SPEED_DRV_100G 0x6
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#define LINK_SPEED_DRV_200G 0x7
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#define LINK_SPEED_DRV_2_5G 0xE
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#define LINK_SPEED_DRV_100M 0xF
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/* nvm cfg 201 - u32 speed_cap_mask */
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#define SPEED_CAPABILITY_DRV_1G 0x1
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#define SPEED_CAPABILITY_DRV_10G 0x2
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#define SPEED_CAPABILITY_DRV_25G 0x4
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#define SPEED_CAPABILITY_DRV_40G 0x8
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#define SPEED_CAPABILITY_DRV_50G 0x10
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#define SPEED_CAPABILITY_DRV_100G 0x20
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#define SPEED_CAPABILITY_DRV_100M 0x8000
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/* nvm cfg 202 */
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/* nvm cfg 205 */
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#define LINK_SPEED_FW_NUM 205
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/* nvm cfg 210 */
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/* nvm cfg 211 */
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/* nvm cfg 213 */
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#define SPEED_DRV_MASK LINK_SPEED_DRV_MASK
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/******************************************************************************
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* Doorbell info.
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*****************************************************************************/
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#define RX_DOORBELL_KEY_RX (0x1UL << 28)
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#define TX_DOORBELL_KEY_TX (0x0UL << 28)
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#define CMPL_DOORBELL_IDX_VALID 0x4000000UL
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#define CMPL_DOORBELL_KEY_CMPL (0x2UL << 28)
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/******************************************************************************
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* Transmit info.
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*****************************************************************************/
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struct tx_bd_short {
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u16 flags_type;
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#define TX_BD_SHORT_TYPE_TX_BD_SHORT 0x0UL
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#define TX_BD_SHORT_FLAGS_PACKET_END 0x40UL
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#define TX_BD_SHORT_FLAGS_NO_CMPL 0x80UL
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#define TX_BD_SHORT_FLAGS_BD_CNT_SFT 8
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#define TX_BD_SHORT_FLAGS_LHINT_LT512 (0x0UL << 13)
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#define TX_BD_SHORT_FLAGS_LHINT_LT1K (0x1UL << 13)
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#define TX_BD_SHORT_FLAGS_LHINT_LT2K (0x2UL << 13)
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#define TX_BD_SHORT_FLAGS_LHINT_GTE2K (0x3UL << 13)
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#define TX_BD_SHORT_FLAGS_COAL_NOW 0x8000UL
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u16 len;
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u32 opaque;
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union dma_addr64_t dma;
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};
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struct lm_tx_info_t {
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void *bd_virt;
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u16 prod_id; /* Tx producer index. */
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u16 cons_id;
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u16 ring_cnt;
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u32 cnt; /* Tx statistics. */
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u32 cnt_req;
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};
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struct cmpl_base {
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u16 type;
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#define CMPL_BASE_TYPE_MASK 0x3fUL
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#define CMPL_BASE_TYPE_TX_L2 0x0UL
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#define CMPL_BASE_TYPE_RX_L2 0x11UL
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#define CMPL_BASE_TYPE_STAT_EJECT 0x1aUL
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#define CMPL_BASE_TYPE_HWRM_ASYNC_EVENT 0x2eUL
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u16 info1;
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u32 info2;
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u32 info3_v;
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#define CMPL_BASE_V 0x1UL
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u32 info4;
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};
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struct lm_cmp_info_t {
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void *bd_virt;
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u16 cons_idx;
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u16 ring_cnt;
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u8 completion_bit;
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u8 res[3];
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};
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struct rx_pkt_cmpl {
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u16 flags_type;
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u16 len;
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u32 opaque;
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u8 agg_bufs_v1;
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u8 rss_hash_type;
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u8 payload_offset;
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u8 unused1;
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u32 rss_hash;
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};
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struct rx_pkt_cmpl_hi {
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u32 flags2;
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u32 metadata;
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u16 errors_v2;
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#define RX_PKT_CMPL_V2 0x1UL
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#define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_SFT 1
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u16 cfa_code;
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u32 reorder;
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};
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struct rx_prod_pkt_bd {
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u16 flags_type;
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#define RX_PROD_PKT_BD_TYPE_RX_PROD_PKT 0x4UL
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u16 len;
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u32 opaque;
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union dma_addr64_t dma;
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};
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struct lm_rx_info_t {
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void *bd_virt;
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void *iob[NUM_RX_BUFFERS];
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void *iob_rx;
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u16 iob_len;
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u16 iob_recv;
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u16 iob_cnt;
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u16 buf_cnt; /* Total Rx buffer descriptors. */
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u16 ring_cnt;
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u16 cons_idx; /* Last processed consumer index. */
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u32 rx_cnt;
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u32 rx_buf_cnt;
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u32 err;
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u32 crc;
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u32 dropped;
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};
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#define VALID_DRIVER_REG 0x0001
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#define VALID_STAT_CTX 0x0002
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#define VALID_RING_CQ 0x0004
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#define VALID_RING_TX 0x0008
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#define VALID_RING_RX 0x0010
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#define VALID_RING_GRP 0x0020
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#define VALID_VNIC_ID 0x0040
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#define VALID_RX_IOB 0x0080
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#define VALID_L2_FILTER 0x0100
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enum RX_FLAGS {
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PKT_DONE = 0,
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PKT_RECEIVED = 1,
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PKT_DROPPED = 2,
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};
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struct bnxt {
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struct udevice *pdev;
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const char *name;
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unsigned int cardnum;
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void *hwrm_addr_req;
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void *hwrm_addr_resp;
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void *hwrm_addr_data;
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dma_addr_t data_addr_mapping;
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dma_addr_t req_addr_mapping;
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dma_addr_t resp_addr_mapping;
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struct lm_tx_info_t tx; /* Tx info. */
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struct lm_rx_info_t rx; /* Rx info. */
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struct lm_cmp_info_t cq; /* completion info. */
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u16 last_resp_code;
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u16 seq_id;
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u32 flag_hwrm;
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u32 flags;
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u16 vendor_id;
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u16 device_id;
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u16 subsystem_vendor;
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u16 subsystem_device;
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u16 cmd_reg;
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u8 irq;
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void __iomem *bar0;
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void __iomem *bar1;
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void __iomem *bar2;
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u16 chip_num;
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/* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
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u32 chip_id;
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u32 hwrm_cmd_timeout;
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u16 hwrm_spec_code;
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u16 hwrm_max_req_len;
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u16 hwrm_max_ext_req_len;
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u8 fw_maj;
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u8 fw_min;
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u8 fw_bld;
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u8 fw_rsvd;
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u8 mac_addr[ETH_ALEN]; /* HW MAC address */
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u8 mac_set[ETH_ALEN]; /* NVM Configured MAC */
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u16 fid;
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u8 port_idx;
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u8 ordinal_value;
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u16 mtu;
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u16 ring_grp_id;
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u16 cq_ring_id;
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u16 tx_ring_id;
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u16 rx_ring_id;
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u16 current_link_speed;
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u16 link_status;
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u16 wait_link_timeout;
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u64 l2_filter_id;
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u16 vnic_id;
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u16 stat_ctx_id;
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u32 medium;
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u16 support_speeds;
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u32 link_set;
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u8 media_detect;
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u8 media_change;
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u16 max_vfs;
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u16 vf_res_strategy;
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u16 min_vnics;
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u16 max_vnics;
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u16 max_msix;
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u16 min_hw_ring_grps;
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u16 max_hw_ring_grps;
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u16 min_tx_rings;
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u16 max_tx_rings;
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u16 min_rx_rings;
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u16 max_rx_rings;
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u16 min_cp_rings;
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u16 max_cp_rings;
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u16 min_rsscos_ctxs;
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u16 max_rsscos_ctxs;
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u16 min_l2_ctxs;
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u16 max_l2_ctxs;
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u16 min_stat_ctxs;
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u16 max_stat_ctxs;
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u16 num_cmpl_rings;
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u16 num_tx_rings;
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u16 num_rx_rings;
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u16 num_stat_ctxs;
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u16 num_hw_ring_grps;
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bool card_en;
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};
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#define SHORT_CMD_SUPPORTED VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED
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#define SHORT_CMD_REQUIRED VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_REQUIRED
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#define CQ_DOORBELL_KEY_IDX(a) \
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(CMPL_DOORBELL_KEY_CMPL | \
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CMPL_DOORBELL_IDX_VALID | \
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(u32)(a))
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#define TX_BD_FLAGS \
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(TX_BD_SHORT_TYPE_TX_BD_SHORT | \
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TX_BD_SHORT_FLAGS_NO_CMPL | \
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TX_BD_SHORT_FLAGS_COAL_NOW | \
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TX_BD_SHORT_FLAGS_PACKET_END | \
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(1 << TX_BD_SHORT_FLAGS_BD_CNT_SFT))
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#define MEM_HWRM_RESP memalign(BNXT_DMA_ALIGNMENT, RESP_BUF_SIZE_ALIGNED)
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#define PORT_PHY_FLAGS (BNXT_FLAG_NPAR_MODE | BNXT_FLAG_MULTI_HOST)
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#define RING_FREE(bp, rid, flag) bnxt_hwrm_ring_free(bp, rid, flag)
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#define QCFG_PHY_ALL (SUPPORT_SPEEDS | DETECT_MEDIA | PHY_SPEED | PHY_STATUS)
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#endif /* _BNXT_H_ */
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