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https://github.com/AsahiLinux/u-boot
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b2e0889aba
This function always succeeds, so don't check its return value. Signed-off-by: Sean Anderson <seanga2@gmail.com> Link: https://lore.kernel.org/r/20220115222504.617013-4-seanga2@gmail.com
639 lines
15 KiB
C
639 lines
15 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2018 Álvaro Fernández Rojas <noltari@gmail.com>
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*
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* Derived from linux/drivers/net/ethernet/broadcom/bcm63xx_enet.c:
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* Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
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*/
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#include <common.h>
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#include <clk.h>
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#include <dm.h>
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#include <dma.h>
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#include <log.h>
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#include <malloc.h>
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#include <miiphy.h>
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#include <net.h>
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#include <reset.h>
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#include <wait_bit.h>
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#include <asm/io.h>
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#include <dm/device_compat.h>
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#include <linux/delay.h>
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#define ETH_PORT_STR "brcm,enetsw-port"
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#define ETH_RX_DESC PKTBUFSRX
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#define ETH_ZLEN 60
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#define ETH_TIMEOUT 100
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#define ETH_MAX_PORT 8
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#define ETH_RGMII_PORT0 4
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/* Port traffic control */
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#define ETH_PTCTRL_REG(x) (0x0 + (x))
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#define ETH_PTCTRL_RXDIS_SHIFT 0
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#define ETH_PTCTRL_RXDIS_MASK (1 << ETH_PTCTRL_RXDIS_SHIFT)
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#define ETH_PTCTRL_TXDIS_SHIFT 1
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#define ETH_PTCTRL_TXDIS_MASK (1 << ETH_PTCTRL_TXDIS_SHIFT)
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/* Switch mode register */
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#define ETH_SWMODE_REG 0xb
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#define ETH_SWMODE_FWD_EN_SHIFT 1
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#define ETH_SWMODE_FWD_EN_MASK (1 << ETH_SWMODE_FWD_EN_SHIFT)
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/* IMP override Register */
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#define ETH_IMPOV_REG 0xe
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#define ETH_IMPOV_LINKUP_SHIFT 0
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#define ETH_IMPOV_LINKUP_MASK (1 << ETH_IMPOV_LINKUP_SHIFT)
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#define ETH_IMPOV_FDX_SHIFT 1
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#define ETH_IMPOV_FDX_MASK (1 << ETH_IMPOV_FDX_SHIFT)
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#define ETH_IMPOV_100_SHIFT 2
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#define ETH_IMPOV_100_MASK (1 << ETH_IMPOV_100_SHIFT)
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#define ETH_IMPOV_1000_SHIFT 3
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#define ETH_IMPOV_1000_MASK (1 << ETH_IMPOV_1000_SHIFT)
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#define ETH_IMPOV_RXFLOW_SHIFT 4
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#define ETH_IMPOV_RXFLOW_MASK (1 << ETH_IMPOV_RXFLOW_SHIFT)
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#define ETH_IMPOV_TXFLOW_SHIFT 5
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#define ETH_IMPOV_TXFLOW_MASK (1 << ETH_IMPOV_TXFLOW_SHIFT)
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#define ETH_IMPOV_FORCE_SHIFT 7
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#define ETH_IMPOV_FORCE_MASK (1 << ETH_IMPOV_FORCE_SHIFT)
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/* Port override Register */
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#define ETH_PORTOV_REG(x) (0x58 + (x))
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#define ETH_PORTOV_LINKUP_SHIFT 0
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#define ETH_PORTOV_LINKUP_MASK (1 << ETH_PORTOV_LINKUP_SHIFT)
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#define ETH_PORTOV_FDX_SHIFT 1
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#define ETH_PORTOV_FDX_MASK (1 << ETH_PORTOV_FDX_SHIFT)
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#define ETH_PORTOV_100_SHIFT 2
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#define ETH_PORTOV_100_MASK (1 << ETH_PORTOV_100_SHIFT)
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#define ETH_PORTOV_1000_SHIFT 3
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#define ETH_PORTOV_1000_MASK (1 << ETH_PORTOV_1000_SHIFT)
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#define ETH_PORTOV_RXFLOW_SHIFT 4
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#define ETH_PORTOV_RXFLOW_MASK (1 << ETH_PORTOV_RXFLOW_SHIFT)
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#define ETH_PORTOV_TXFLOW_SHIFT 5
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#define ETH_PORTOV_TXFLOW_MASK (1 << ETH_PORTOV_TXFLOW_SHIFT)
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#define ETH_PORTOV_ENABLE_SHIFT 6
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#define ETH_PORTOV_ENABLE_MASK (1 << ETH_PORTOV_ENABLE_SHIFT)
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/* Port RGMII control register */
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#define ETH_RGMII_CTRL_REG(x) (0x60 + (x))
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#define ETH_RGMII_CTRL_GMII_CLK_EN (1 << 7)
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#define ETH_RGMII_CTRL_MII_OVERRIDE_EN (1 << 6)
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#define ETH_RGMII_CTRL_MII_MODE_MASK (3 << 4)
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#define ETH_RGMII_CTRL_RGMII_MODE (0 << 4)
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#define ETH_RGMII_CTRL_MII_MODE (1 << 4)
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#define ETH_RGMII_CTRL_RVMII_MODE (2 << 4)
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#define ETH_RGMII_CTRL_TIMING_SEL_EN (1 << 0)
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/* Port RGMII timing register */
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#define ENETSW_RGMII_TIMING_REG(x) (0x68 + (x))
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/* MDIO control register */
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#define MII_SC_REG 0xb0
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#define MII_SC_EXT_SHIFT 16
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#define MII_SC_EXT_MASK (1 << MII_SC_EXT_SHIFT)
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#define MII_SC_REG_SHIFT 20
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#define MII_SC_PHYID_SHIFT 25
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#define MII_SC_RD_SHIFT 30
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#define MII_SC_RD_MASK (1 << MII_SC_RD_SHIFT)
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#define MII_SC_WR_SHIFT 31
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#define MII_SC_WR_MASK (1 << MII_SC_WR_SHIFT)
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/* MDIO data register */
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#define MII_DAT_REG 0xb4
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/* Global Management Configuration Register */
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#define ETH_GMCR_REG 0x200
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#define ETH_GMCR_RST_MIB_SHIFT 0
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#define ETH_GMCR_RST_MIB_MASK (1 << ETH_GMCR_RST_MIB_SHIFT)
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/* Jumbo control register port mask register */
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#define ETH_JMBCTL_PORT_REG 0x4004
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/* Jumbo control mib good frame register */
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#define ETH_JMBCTL_MAXSIZE_REG 0x4008
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/* ETH port data */
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struct bcm_enetsw_port {
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bool used;
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const char *name;
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/* Config */
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bool bypass_link;
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int force_speed;
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bool force_duplex_full;
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/* PHY */
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int phy_id;
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};
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/* ETH data */
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struct bcm6368_eth_priv {
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void __iomem *base;
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/* DMA */
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struct dma rx_dma;
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struct dma tx_dma;
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/* Ports */
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uint8_t num_ports;
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struct bcm_enetsw_port used_ports[ETH_MAX_PORT];
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int sw_port_link[ETH_MAX_PORT];
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bool rgmii_override;
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bool rgmii_timing;
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/* PHY */
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int phy_id;
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};
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static inline bool bcm_enet_port_is_rgmii(int portid)
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{
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return portid >= ETH_RGMII_PORT0;
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}
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static int bcm6368_mdio_read(struct bcm6368_eth_priv *priv, uint8_t ext,
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int phy_id, int reg)
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{
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uint32_t val;
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writel_be(0, priv->base + MII_SC_REG);
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val = MII_SC_RD_MASK |
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(phy_id << MII_SC_PHYID_SHIFT) |
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(reg << MII_SC_REG_SHIFT);
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if (ext)
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val |= MII_SC_EXT_MASK;
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writel_be(val, priv->base + MII_SC_REG);
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udelay(50);
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return readw_be(priv->base + MII_DAT_REG);
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}
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static int bcm6368_mdio_write(struct bcm6368_eth_priv *priv, uint8_t ext,
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int phy_id, int reg, u16 data)
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{
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uint32_t val;
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writel_be(0, priv->base + MII_SC_REG);
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val = MII_SC_WR_MASK |
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(phy_id << MII_SC_PHYID_SHIFT) |
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(reg << MII_SC_REG_SHIFT);
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if (ext)
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val |= MII_SC_EXT_MASK;
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val |= data;
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writel_be(val, priv->base + MII_SC_REG);
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udelay(50);
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return 0;
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}
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static int bcm6368_eth_free_pkt(struct udevice *dev, uchar *packet, int len)
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{
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struct bcm6368_eth_priv *priv = dev_get_priv(dev);
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return dma_prepare_rcv_buf(&priv->rx_dma, packet, len);
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}
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static int bcm6368_eth_recv(struct udevice *dev, int flags, uchar **packetp)
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{
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struct bcm6368_eth_priv *priv = dev_get_priv(dev);
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return dma_receive(&priv->rx_dma, (void**)packetp, NULL);
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}
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static int bcm6368_eth_send(struct udevice *dev, void *packet, int length)
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{
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struct bcm6368_eth_priv *priv = dev_get_priv(dev);
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/* pad packets smaller than ETH_ZLEN */
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if (length < ETH_ZLEN) {
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memset(packet + length, 0, ETH_ZLEN - length);
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length = ETH_ZLEN;
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}
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return dma_send(&priv->tx_dma, packet, length, NULL);
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}
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static int bcm6368_eth_adjust_link(struct udevice *dev)
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{
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struct bcm6368_eth_priv *priv = dev_get_priv(dev);
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unsigned int i;
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for (i = 0; i < priv->num_ports; i++) {
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struct bcm_enetsw_port *port;
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int val, j, up, adv, lpa, speed, duplex, media;
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int external_phy = bcm_enet_port_is_rgmii(i);
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u8 override;
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port = &priv->used_ports[i];
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if (!port->used)
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continue;
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if (port->bypass_link)
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continue;
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/* dummy read to clear */
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for (j = 0; j < 2; j++)
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val = bcm6368_mdio_read(priv, external_phy,
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port->phy_id, MII_BMSR);
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if (val == 0xffff)
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continue;
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up = (val & BMSR_LSTATUS) ? 1 : 0;
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if (!(up ^ priv->sw_port_link[i]))
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continue;
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priv->sw_port_link[i] = up;
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/* link changed */
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if (!up) {
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dev_info(dev, "link DOWN on %s\n", port->name);
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writeb_be(ETH_PORTOV_ENABLE_MASK,
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priv->base + ETH_PORTOV_REG(i));
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writeb_be(ETH_PTCTRL_RXDIS_MASK |
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ETH_PTCTRL_TXDIS_MASK,
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priv->base + ETH_PTCTRL_REG(i));
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continue;
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}
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adv = bcm6368_mdio_read(priv, external_phy,
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port->phy_id, MII_ADVERTISE);
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lpa = bcm6368_mdio_read(priv, external_phy, port->phy_id,
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MII_LPA);
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/* figure out media and duplex from advertise and LPA values */
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media = mii_nway_result(lpa & adv);
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duplex = (media & ADVERTISE_FULL) ? 1 : 0;
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if (media & (ADVERTISE_100FULL | ADVERTISE_100HALF))
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speed = 100;
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else
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speed = 10;
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if (val & BMSR_ESTATEN) {
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adv = bcm6368_mdio_read(priv, external_phy,
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port->phy_id, MII_CTRL1000);
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lpa = bcm6368_mdio_read(priv, external_phy,
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port->phy_id, MII_STAT1000);
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if ((adv & (ADVERTISE_1000FULL | ADVERTISE_1000HALF)) &&
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(lpa & (LPA_1000FULL | LPA_1000HALF))) {
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speed = 1000;
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duplex = (lpa & LPA_1000FULL);
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}
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}
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pr_alert("link UP on %s, %dMbps, %s-duplex\n",
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port->name, speed, duplex ? "full" : "half");
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override = ETH_PORTOV_ENABLE_MASK |
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ETH_PORTOV_LINKUP_MASK;
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if (speed == 1000)
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override |= ETH_PORTOV_1000_MASK;
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else if (speed == 100)
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override |= ETH_PORTOV_100_MASK;
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if (duplex)
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override |= ETH_PORTOV_FDX_MASK;
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writeb_be(override, priv->base + ETH_PORTOV_REG(i));
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writeb_be(0, priv->base + ETH_PTCTRL_REG(i));
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}
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return 0;
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}
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static int bcm6368_eth_start(struct udevice *dev)
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{
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struct bcm6368_eth_priv *priv = dev_get_priv(dev);
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uint8_t i;
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/* disable all ports */
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for (i = 0; i < priv->num_ports; i++) {
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setbits_8(priv->base + ETH_PORTOV_REG(i),
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ETH_PORTOV_ENABLE_MASK);
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setbits_8(priv->base + ETH_PTCTRL_REG(i),
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ETH_PTCTRL_RXDIS_MASK | ETH_PTCTRL_TXDIS_MASK);
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priv->sw_port_link[i] = 0;
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}
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/* enable external ports */
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for (i = ETH_RGMII_PORT0; i < priv->num_ports; i++) {
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u8 rgmii_ctrl = ETH_RGMII_CTRL_GMII_CLK_EN;
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if (!priv->used_ports[i].used)
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continue;
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if (priv->rgmii_override)
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rgmii_ctrl |= ETH_RGMII_CTRL_MII_OVERRIDE_EN;
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if (priv->rgmii_timing)
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rgmii_ctrl |= ETH_RGMII_CTRL_TIMING_SEL_EN;
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setbits_8(priv->base + ETH_RGMII_CTRL_REG(i), rgmii_ctrl);
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}
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/* reset mib */
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setbits_8(priv->base + ETH_GMCR_REG, ETH_GMCR_RST_MIB_MASK);
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mdelay(1);
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clrbits_8(priv->base + ETH_GMCR_REG, ETH_GMCR_RST_MIB_MASK);
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mdelay(1);
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/* force CPU port state */
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setbits_8(priv->base + ETH_IMPOV_REG,
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ETH_IMPOV_FORCE_MASK | ETH_IMPOV_LINKUP_MASK);
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/* enable switch forward engine */
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setbits_8(priv->base + ETH_SWMODE_REG, ETH_SWMODE_FWD_EN_MASK);
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/* prepare rx dma buffers */
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for (i = 0; i < ETH_RX_DESC; i++) {
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int ret = dma_prepare_rcv_buf(&priv->rx_dma, net_rx_packets[i],
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PKTSIZE_ALIGN);
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if (ret < 0)
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break;
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}
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/* enable dma rx channel */
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dma_enable(&priv->rx_dma);
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/* enable dma tx channel */
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dma_enable(&priv->tx_dma);
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/* apply override config for bypass_link ports here. */
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for (i = 0; i < priv->num_ports; i++) {
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struct bcm_enetsw_port *port;
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u8 override;
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port = &priv->used_ports[i];
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if (!port->used)
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continue;
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if (!port->bypass_link)
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continue;
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override = ETH_PORTOV_ENABLE_MASK |
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ETH_PORTOV_LINKUP_MASK;
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switch (port->force_speed) {
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case 1000:
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override |= ETH_PORTOV_1000_MASK;
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break;
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case 100:
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override |= ETH_PORTOV_100_MASK;
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break;
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case 10:
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break;
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default:
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pr_warn("%s: invalid forced speed on port %s\n",
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__func__, port->name);
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break;
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}
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if (port->force_duplex_full)
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override |= ETH_PORTOV_FDX_MASK;
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writeb_be(override, priv->base + ETH_PORTOV_REG(i));
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writeb_be(0, priv->base + ETH_PTCTRL_REG(i));
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}
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bcm6368_eth_adjust_link(dev);
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return 0;
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}
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static void bcm6368_eth_stop(struct udevice *dev)
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{
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struct bcm6368_eth_priv *priv = dev_get_priv(dev);
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uint8_t i;
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/* disable all ports */
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for (i = 0; i < priv->num_ports; i++) {
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setbits_8(priv->base + ETH_PORTOV_REG(i),
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ETH_PORTOV_ENABLE_MASK);
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setbits_8(priv->base + ETH_PTCTRL_REG(i),
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ETH_PTCTRL_RXDIS_MASK | ETH_PTCTRL_TXDIS_MASK);
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}
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/* disable external ports */
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for (i = ETH_RGMII_PORT0; i < priv->num_ports; i++) {
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if (!priv->used_ports[i].used)
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continue;
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clrbits_8(priv->base + ETH_RGMII_CTRL_REG(i),
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ETH_RGMII_CTRL_GMII_CLK_EN);
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}
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/* disable CPU port */
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clrbits_8(priv->base + ETH_IMPOV_REG,
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ETH_IMPOV_FORCE_MASK | ETH_IMPOV_LINKUP_MASK);
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/* disable switch forward engine */
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clrbits_8(priv->base + ETH_SWMODE_REG, ETH_SWMODE_FWD_EN_MASK);
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/* disable dma rx channel */
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dma_disable(&priv->rx_dma);
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/* disable dma tx channel */
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dma_disable(&priv->tx_dma);
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}
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static const struct eth_ops bcm6368_eth_ops = {
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.free_pkt = bcm6368_eth_free_pkt,
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.recv = bcm6368_eth_recv,
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.send = bcm6368_eth_send,
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.start = bcm6368_eth_start,
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.stop = bcm6368_eth_stop,
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};
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static const struct udevice_id bcm6368_eth_ids[] = {
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{ .compatible = "brcm,bcm6368-enet", },
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{ /* sentinel */ }
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};
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static bool bcm6368_phy_is_external(struct bcm6368_eth_priv *priv, int phy_id)
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{
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uint8_t i;
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for (i = 0; i < priv->num_ports; ++i) {
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if (!priv->used_ports[i].used)
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continue;
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if (priv->used_ports[i].phy_id == phy_id)
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return bcm_enet_port_is_rgmii(i);
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}
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return true;
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}
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static int bcm6368_mii_mdio_read(struct mii_dev *bus, int addr, int devaddr,
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int reg)
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{
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struct bcm6368_eth_priv *priv = bus->priv;
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bool ext = bcm6368_phy_is_external(priv, addr);
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return bcm6368_mdio_read(priv, ext, addr, reg);
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}
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static int bcm6368_mii_mdio_write(struct mii_dev *bus, int addr, int devaddr,
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int reg, u16 data)
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{
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struct bcm6368_eth_priv *priv = bus->priv;
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bool ext = bcm6368_phy_is_external(priv, addr);
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return bcm6368_mdio_write(priv, ext, addr, reg, data);
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}
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static int bcm6368_mdio_init(const char *name, struct bcm6368_eth_priv *priv)
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{
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struct mii_dev *bus;
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bus = mdio_alloc();
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if (!bus) {
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pr_err("%s: failed to allocate MDIO bus\n", __func__);
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return -ENOMEM;
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}
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bus->read = bcm6368_mii_mdio_read;
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bus->write = bcm6368_mii_mdio_write;
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bus->priv = priv;
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snprintf(bus->name, sizeof(bus->name), "%s", name);
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return mdio_register(bus);
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}
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static int bcm6368_eth_probe(struct udevice *dev)
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{
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struct eth_pdata *pdata = dev_get_plat(dev);
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struct bcm6368_eth_priv *priv = dev_get_priv(dev);
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int num_ports, ret, i;
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ofnode node;
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/* get base address */
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priv->base = dev_remap_addr(dev);
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if (!priv->base)
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return -EINVAL;
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pdata->iobase = (phys_addr_t) priv->base;
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/* get number of ports */
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num_ports = dev_read_u32_default(dev, "brcm,num-ports", ETH_MAX_PORT);
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if (!num_ports || num_ports > ETH_MAX_PORT)
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return -EINVAL;
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/* get dma channels */
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ret = dma_get_by_name(dev, "tx", &priv->tx_dma);
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if (ret)
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return -EINVAL;
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ret = dma_get_by_name(dev, "rx", &priv->rx_dma);
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if (ret)
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return -EINVAL;
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/* try to enable clocks */
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for (i = 0; ; i++) {
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struct clk clk;
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int ret;
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ret = clk_get_by_index(dev, i, &clk);
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if (ret < 0)
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break;
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|
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ret = clk_enable(&clk);
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if (ret < 0) {
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pr_err("%s: error enabling clock %d\n", __func__, i);
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return ret;
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}
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clk_free(&clk);
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}
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|
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/* try to perform resets */
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for (i = 0; ; i++) {
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struct reset_ctl reset;
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int ret;
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ret = reset_get_by_index(dev, i, &reset);
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if (ret < 0)
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break;
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|
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ret = reset_deassert(&reset);
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if (ret < 0) {
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pr_err("%s: error deasserting reset %d\n", __func__, i);
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return ret;
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}
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|
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ret = reset_free(&reset);
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if (ret < 0) {
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pr_err("%s: error freeing reset %d\n", __func__, i);
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return ret;
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}
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}
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|
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/* set priv data */
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priv->num_ports = num_ports;
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if (dev_read_bool(dev, "brcm,rgmii-override"))
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priv->rgmii_override = true;
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if (dev_read_bool(dev, "brcm,rgmii-timing"))
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priv->rgmii_timing = true;
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|
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/* get ports */
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dev_for_each_subnode(node, dev) {
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const char *comp;
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const char *label;
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|
unsigned int p;
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|
int phy_id;
|
|
int speed;
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|
|
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comp = ofnode_read_string(node, "compatible");
|
|
if (!comp || memcmp(comp, ETH_PORT_STR, sizeof(ETH_PORT_STR)))
|
|
continue;
|
|
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p = ofnode_read_u32_default(node, "reg", ETH_MAX_PORT);
|
|
if (p >= num_ports)
|
|
return -EINVAL;
|
|
|
|
label = ofnode_read_string(node, "label");
|
|
if (!label) {
|
|
debug("%s: node %s has no label\n", __func__,
|
|
ofnode_get_name(node));
|
|
return -EINVAL;
|
|
}
|
|
|
|
phy_id = ofnode_read_u32_default(node, "brcm,phy-id", -1);
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|
|
|
priv->used_ports[p].used = true;
|
|
priv->used_ports[p].name = label;
|
|
priv->used_ports[p].phy_id = phy_id;
|
|
|
|
if (ofnode_read_bool(node, "full-duplex"))
|
|
priv->used_ports[p].force_duplex_full = true;
|
|
if (ofnode_read_bool(node, "bypass-link"))
|
|
priv->used_ports[p].bypass_link = true;
|
|
speed = ofnode_read_u32_default(node, "speed", 0);
|
|
if (speed)
|
|
priv->used_ports[p].force_speed = speed;
|
|
}
|
|
|
|
/* init mii bus */
|
|
ret = bcm6368_mdio_init(dev->name, priv);
|
|
if (ret)
|
|
return ret;
|
|
|
|
/* enable jumbo on all ports */
|
|
writel_be(0x1ff, priv->base + ETH_JMBCTL_PORT_REG);
|
|
writew_be(9728, priv->base + ETH_JMBCTL_MAXSIZE_REG);
|
|
|
|
return 0;
|
|
}
|
|
|
|
U_BOOT_DRIVER(bcm6368_eth) = {
|
|
.name = "bcm6368_eth",
|
|
.id = UCLASS_ETH,
|
|
.of_match = bcm6368_eth_ids,
|
|
.ops = &bcm6368_eth_ops,
|
|
.plat_auto = sizeof(struct eth_pdata),
|
|
.priv_auto = sizeof(struct bcm6368_eth_priv),
|
|
.probe = bcm6368_eth_probe,
|
|
};
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