mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-25 20:43:32 +00:00
506df9dc58
1. Convert all linker symbols to char[] type so that we can get the
corresponding address by calling array name 'var' or its address
'&var'. In this way, we can avoid some potential issues[1].
2. Remove unused symbol '_TEXT_BASE'. It has been abandoned and has
not been referenced by any source code.
3. Move '__data_end' to the arch x86's own sections header as it's
only used by x86 arch.
4. Remove some duplicate declared linker symbols. Now we use the
standard header file to declare them.
[1] This patch fixes the boot failure on MIPS target. Error log:
SPL: Image overlaps SPL
Fixes: 1b8a1be1a1 ("spl: spl_legacy: Fix spl_end address")
Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
381 lines
9.2 KiB
C
381 lines
9.2 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2021 Gateworks Corporation
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*/
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#include <common.h>
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#include <cpu_func.h>
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#include <hang.h>
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#include <i2c.h>
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#include <init.h>
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#include <spl.h>
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#include <asm/mach-imx/gpio.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/imx8mm_pins.h>
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#include <asm/arch/imx8mn_pins.h>
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#include <asm/arch/imx8mp_pins.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/mach-imx/boot_mode.h>
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#include <asm/mach-imx/mxc_i2c.h>
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#include <asm/arch/ddr.h>
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#include <asm-generic/gpio.h>
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#include <asm/sections.h>
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#include <dm/uclass.h>
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#include <dm/device.h>
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#include <dm/pinctrl.h>
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#include <linux/delay.h>
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#include <power/bd71837.h>
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#include <power/mp5416.h>
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#include <power/pca9450.h>
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#include "eeprom.h"
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#include "lpddr4_timing.h"
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#define PCIE_RSTN IMX_GPIO_NR(4, 6)
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static void spl_dram_init(int size)
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{
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struct dram_timing_info *dram_timing;
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switch (size) {
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#ifdef CONFIG_IMX8MM
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case 512:
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dram_timing = &dram_timing_512mb;
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break;
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case 1024:
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dram_timing = &dram_timing_1gb;
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break;
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case 2048:
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dram_timing = &dram_timing_2gb;
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break;
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case 4096:
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dram_timing = &dram_timing_4gb;
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break;
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default:
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printf("Unknown DDR configuration: %d MiB\n", size);
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dram_timing = &dram_timing_1gb;
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size = 1024;
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#elif CONFIG_IMX8MN
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case 1024:
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dram_timing = &dram_timing_1gb_single_die;
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break;
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case 2048:
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if (!strcmp(eeprom_get_model(), "GW7902-SP466-A") ||
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!strcmp(eeprom_get_model(), "GW7902-SP466-B")) {
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dram_timing = &dram_timing_2gb_dual_die;
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} else {
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dram_timing = &dram_timing_2gb_single_die;
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}
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break;
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default:
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printf("Unknown DDR configuration: %d MiB\n", size);
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dram_timing = &dram_timing_2gb_dual_die;
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size = 2048;
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#elif CONFIG_IMX8MP
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case 1024:
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dram_timing = &dram_timing_1gb_single_die;
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break;
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case 4096:
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dram_timing = &dram_timing_4gb_dual_die;
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break;
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default:
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printf("Unknown DDR configuration: %d GiB\n", size);
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dram_timing = &dram_timing_4gb_dual_die;
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size = 4096;
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#endif
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}
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printf("DRAM : LPDDR4 ");
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if (size > 512)
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printf("%d GiB", size / 1024);
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else
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printf("%d MiB", size);
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printf(" %dMT/s %dMHz\n",
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dram_timing->fsp_msg[0].drate,
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dram_timing->fsp_msg[0].drate / 2);
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ddr_init(dram_timing);
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}
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/*
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* Model specific PMIC adjustments necessary prior to DRAM init
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*
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* Note that we can not use pmic dm drivers here as we have a generic
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* venice dt that does not have board-specific pmic's defined.
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*
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* Instead we must use dm_i2c so we a helpers to give us
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* clrsetbit functions we would otherwise have if we could use PMIC dm
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* drivers.
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*/
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static int dm_i2c_clrsetbits(struct udevice *dev, uint reg, uint clr, uint set)
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{
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int ret;
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u8 val;
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ret = dm_i2c_read(dev, reg, &val, 1);
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if (ret)
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return ret;
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val = (val & ~clr) | set;
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return dm_i2c_write(dev, reg, &val, 1);
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}
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static int power_init_board(void)
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{
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const char *model = eeprom_get_model();
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struct udevice *bus;
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struct udevice *dev;
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int ret;
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if ((!strncmp(model, "GW71", 4)) ||
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(!strncmp(model, "GW72", 4)) ||
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(!strncmp(model, "GW73", 4)) ||
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(!strncmp(model, "GW7905", 6))) {
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ret = uclass_get_device_by_seq(UCLASS_I2C, 0, &bus);
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if (ret) {
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printf("PMIC : failed I2C1 probe: %d\n", ret);
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return ret;
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}
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ret = dm_i2c_probe(bus, 0x69, 0, &dev);
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if (ret) {
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printf("PMIC : failed probe: %d\n", ret);
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return ret;
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}
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#ifdef CONFIG_IMX8MM
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puts("PMIC : MP5416 (IMX8MM)\n");
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/* set VDD_ARM SW3 to 0.92V for 1.6GHz */
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dm_i2c_reg_write(dev, MP5416_VSET_SW3,
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BIT(7) | MP5416_VSET_SW3_SVAL(920000));
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#elif CONFIG_IMX8MP
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puts("PMIC : MP5416 (IMX8MP)\n");
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/* set VDD_ARM SW3 to 0.95V for 1.6GHz */
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dm_i2c_reg_write(dev, MP5416_VSET_SW3,
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BIT(7) | MP5416_VSET_SW3_SVAL(950000));
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/* set VDD_SOC SW1 to 0.95V for 1.6GHz */
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dm_i2c_reg_write(dev, MP5416_VSET_SW1,
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BIT(7) | MP5416_VSET_SW1_SVAL(950000));
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#endif
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}
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else if (!strncmp(model, "GW74", 4)) {
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ret = uclass_get_device_by_seq(UCLASS_I2C, 0, &bus);
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if (ret) {
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printf("PMIC : failed I2C1 probe: %d\n", ret);
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return ret;
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}
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ret = dm_i2c_probe(bus, 0x25, 0, &dev);
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if (ret) {
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printf("PMIC : failed probe: %d\n", ret);
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return ret;
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}
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puts("PMIC : PCA9450\n");
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/* BUCKxOUT_DVS0/1 control BUCK123 output */
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dm_i2c_reg_write(dev, PCA9450_BUCK123_DVS, 0x29);
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/* Buck 1 DVS control through PMIC_STBY_REQ */
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dm_i2c_reg_write(dev, PCA9450_BUCK1CTRL, 0x59);
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/* Set DVS1 to 0.85v for suspend */
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dm_i2c_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x14);
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/* increase VDD_SOC to 0.95V before first DRAM access */
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dm_i2c_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x1C);
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/* Kernel uses OD/OD freq for SOC */
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/* To avoid timing risk from SOC to ARM, increase VDD_ARM to OD voltage 0.95v */
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dm_i2c_reg_write(dev, PCA9450_BUCK2OUT_DVS0, 0x1C);
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}
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else if ((!strncmp(model, "GW7901", 6)) ||
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(!strncmp(model, "GW7902", 6)) ||
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(!strncmp(model, "GW7903", 6)) ||
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(!strncmp(model, "GW7904", 6))) {
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if (!strncmp(model, "GW7902", 6))
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ret = uclass_get_device_by_seq(UCLASS_I2C, 0, &bus);
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else
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ret = uclass_get_device_by_seq(UCLASS_I2C, 1, &bus);
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if (ret) {
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printf("PMIC : failed I2C2 probe: %d\n", ret);
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return ret;
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}
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ret = dm_i2c_probe(bus, 0x4b, 0, &dev);
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if (ret) {
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printf("PMIC : failed probe: %d\n", ret);
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return ret;
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}
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puts("PMIC : BD71847\n");
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/* unlock the PMIC regs */
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dm_i2c_reg_write(dev, BD718XX_REGLOCK, 0x1);
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/* set switchers to forced PWM mode */
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dm_i2c_clrsetbits(dev, BD718XX_BUCK1_CTRL, 0, 0x8);
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dm_i2c_clrsetbits(dev, BD718XX_BUCK2_CTRL, 0, 0x8);
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dm_i2c_clrsetbits(dev, BD718XX_1ST_NODVS_BUCK_CTRL, 0, 0x8);
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dm_i2c_clrsetbits(dev, BD718XX_2ND_NODVS_BUCK_CTRL, 0, 0x8);
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dm_i2c_clrsetbits(dev, BD718XX_3RD_NODVS_BUCK_CTRL, 0, 0x8);
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dm_i2c_clrsetbits(dev, BD718XX_4TH_NODVS_BUCK_CTRL, 0, 0x8);
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/* increase VDD_0P95 (VDD_GPU/VPU/DRAM) to 0.975v for 1.5Ghz DDR */
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dm_i2c_reg_write(dev, BD718XX_1ST_NODVS_BUCK_VOLT, 0x83);
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/* increase VDD_SOC to 0.85v before first DRAM access */
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dm_i2c_reg_write(dev, BD718XX_BUCK1_VOLT_RUN, 0x0f);
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/* increase VDD_ARM to 0.92v for 800 and 1600Mhz */
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dm_i2c_reg_write(dev, BD718XX_BUCK2_VOLT_RUN, 0x16);
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/* Lock the PMIC regs */
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dm_i2c_reg_write(dev, BD718XX_REGLOCK, 0x11);
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}
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return 0;
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}
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void board_init_f(ulong dummy)
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{
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struct udevice *bus, *dev;
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int i, ret;
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int dram_sz;
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arch_cpu_init();
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init_uart_clk(1);
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timer_init();
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/* Clear the BSS. */
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memset(__bss_start, 0, __bss_end - __bss_start);
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ret = spl_early_init();
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if (ret) {
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debug("spl_early_init() failed: %d\n", ret);
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hang();
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}
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preloader_console_init();
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enable_tzc380();
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/* need to hold PCIe switch in reset otherwise it can lock i2c bus EEPROM is on */
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gpio_request(PCIE_RSTN, "perst#");
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gpio_direction_output(PCIE_RSTN, 0);
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/*
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* probe GSC device
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*
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* On a board with a missing/depleted backup battery for GSC, the
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* board may be ready to probe the GSC before its firmware is
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* running. Wait here for 50ms for the GSC firmware to let go of
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* the SCL/SDA lines to avoid the i2c driver spamming
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* 'Arbitration lost' I2C errors
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*/
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if (!uclass_get_device_by_seq(UCLASS_I2C, 0, &bus)) {
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if (!pinctrl_select_state(bus, "gpio")) {
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struct mxc_i2c_bus *i2c_bus = dev_get_priv(bus);
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struct gpio_desc *scl_gpio = &i2c_bus->scl_gpio;
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struct gpio_desc *sda_gpio = &i2c_bus->sda_gpio;
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dm_gpio_set_dir_flags(scl_gpio, GPIOD_IS_IN);
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dm_gpio_set_dir_flags(sda_gpio, GPIOD_IS_IN);
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for (i = 0; i < 5; i++) {
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if (dm_gpio_get_value(scl_gpio) &&
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dm_gpio_get_value(sda_gpio))
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break;
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mdelay(10);
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}
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pinctrl_select_state(bus, "default");
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}
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}
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/* Wait indefiniately until the GSC probes */
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while (1) {
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if (!uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(gsc), &dev))
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break;
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mdelay(1);
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}
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dram_sz = venice_eeprom_init(0);
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/* PMIC */
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power_init_board();
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/* DDR initialization */
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spl_dram_init(dram_sz);
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board_init_r(NULL, 0);
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}
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/* determine prioritized order of boot devices to load U-Boot from */
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void board_boot_order(u32 *spl_boot_list)
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{
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int i = 0;
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/*
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* If the SPL was loaded via serial loader, we try to get
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* U-Boot proper via USB SDP.
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*/
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if (spl_boot_device() == BOOT_DEVICE_BOARD) {
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#ifdef CONFIG_IMX8MM
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spl_boot_list[i++] = BOOT_DEVICE_BOARD;
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#else
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spl_boot_list[i++] = BOOT_DEVICE_BOOTROM;
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#endif
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}
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/* we have only eMMC in default venice dt */
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spl_boot_list[i++] = BOOT_DEVICE_MMC1;
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}
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/* return boot device based on where the SPL was loaded from */
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int spl_board_boot_device(enum boot_device boot_dev_spl)
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{
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switch (boot_dev_spl) {
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case USB_BOOT:
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return BOOT_DEVICE_BOARD;
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/* SDHC2 */
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case SD2_BOOT:
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case MMC2_BOOT:
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return BOOT_DEVICE_MMC1;
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/* SDHC3 */
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case SD3_BOOT:
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case MMC3_BOOT:
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return BOOT_DEVICE_MMC2;
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default:
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return BOOT_DEVICE_NONE;
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}
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}
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unsigned long spl_mmc_get_uboot_raw_sector(struct mmc *mmc, unsigned long raw_sect)
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{
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if (!IS_SD(mmc)) {
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switch (EXT_CSD_EXTRACT_BOOT_PART(mmc->part_config)) {
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case 1:
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case 2:
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if (IS_ENABLED(CONFIG_IMX8MN) || IS_ENABLED(CONFIG_IMX8MP))
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raw_sect -= 32 * 2;
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break;
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}
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}
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return raw_sect;
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}
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const char *spl_board_loader_name(u32 boot_device)
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{
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switch (boot_device) {
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/* SDHC2 */
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case BOOT_DEVICE_MMC1:
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return "eMMC";
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/* SDHC3 */
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case BOOT_DEVICE_MMC2:
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return "SD card";
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default:
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return NULL;
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}
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}
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void spl_board_init(void)
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{
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arch_misc_init();
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}
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