mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-22 03:03:05 +00:00
42f67fb51c
The boot source node path for emmc is using the old sdhci name.
Replace with correct mmc name and also add same-as-spl to boot order.
Fixes: 0d61f8e5f1 ("rockchip: rk3568: add boot device detection")
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
137 lines
3.6 KiB
C
137 lines
3.6 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2021 Rockchip Electronics Co., Ltd
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*/
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#include <common.h>
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#include <dm.h>
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#include <asm/armv8/mmu.h>
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#include <asm/io.h>
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#include <asm/arch-rockchip/bootrom.h>
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#include <asm/arch-rockchip/grf_rk3568.h>
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#include <asm/arch-rockchip/hardware.h>
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#include <dt-bindings/clock/rk3568-cru.h>
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#define PMUGRF_BASE 0xfdc20000
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#define GRF_BASE 0xfdc60000
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#define GRF_GPIO1B_DS_2 0x218
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#define GRF_GPIO1B_DS_3 0x21c
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#define GRF_GPIO1C_DS_0 0x220
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#define GRF_GPIO1C_DS_1 0x224
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#define GRF_GPIO1C_DS_2 0x228
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#define GRF_GPIO1C_DS_3 0x22c
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#define SGRF_BASE 0xFDD18000
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#define SGRF_SOC_CON4 0x10
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#define EMMC_HPROT_SECURE_CTRL 0x03
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#define SDMMC0_HPROT_SECURE_CTRL 0x01
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#define PMU_BASE_ADDR 0xfdd90000
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#define PMU_NOC_AUTO_CON0 (0x70)
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#define PMU_NOC_AUTO_CON1 (0x74)
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#define EDP_PHY_GRF_BASE 0xfdcb0000
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#define EDP_PHY_GRF_CON0 (EDP_PHY_GRF_BASE + 0x00)
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#define EDP_PHY_GRF_CON10 (EDP_PHY_GRF_BASE + 0x28)
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#define CPU_GRF_BASE 0xfdc30000
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#define GRF_CORE_PVTPLL_CON0 (0x10)
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/* PMU_GRF_GPIO0D_IOMUX_L */
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enum {
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GPIO0D1_SHIFT = 4,
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GPIO0D1_MASK = GENMASK(6, 4),
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GPIO0D1_GPIO = 0,
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GPIO0D1_UART2_TXM0,
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GPIO0D0_SHIFT = 0,
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GPIO0D0_MASK = GENMASK(2, 0),
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GPIO0D0_GPIO = 0,
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GPIO0D0_UART2_RXM0,
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};
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/* GRF_IOFUNC_SEL3 */
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enum {
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UART2_IO_SEL_SHIFT = 10,
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UART2_IO_SEL_MASK = GENMASK(11, 10),
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UART2_IO_SEL_M0 = 0,
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};
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static struct mm_region rk3568_mem_map[] = {
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{
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.virt = 0x0UL,
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.phys = 0x0UL,
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.size = 0xf0000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_INNER_SHARE
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}, {
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.virt = 0xf0000000UL,
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.phys = 0xf0000000UL,
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.size = 0x10000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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.virt = 0x300000000,
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.phys = 0x300000000,
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.size = 0x0c0c00000,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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/* List terminator */
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0,
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}
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};
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const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
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[BROM_BOOTSOURCE_EMMC] = "/mmc@fe310000",
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[BROM_BOOTSOURCE_SPINOR] = "/spi@fe300000/flash@0",
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[BROM_BOOTSOURCE_SD] = "/mmc@fe2b0000",
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};
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struct mm_region *mem_map = rk3568_mem_map;
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void board_debug_uart_init(void)
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{
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static struct rk3568_pmugrf * const pmugrf = (void *)PMUGRF_BASE;
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static struct rk3568_grf * const grf = (void *)GRF_BASE;
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/* UART2 M0 */
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rk_clrsetreg(&grf->iofunc_sel3, UART2_IO_SEL_MASK,
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UART2_IO_SEL_M0 << UART2_IO_SEL_SHIFT);
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/* Switch iomux */
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rk_clrsetreg(&pmugrf->pmu_gpio0d_iomux_l,
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GPIO0D1_MASK | GPIO0D0_MASK,
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GPIO0D1_UART2_TXM0 << GPIO0D1_SHIFT |
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GPIO0D0_UART2_RXM0 << GPIO0D0_SHIFT);
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}
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int arch_cpu_init(void)
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{
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#ifdef CONFIG_SPL_BUILD
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/*
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* When perform idle operation, corresponding clock can
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* be opened or gated automatically.
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*/
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writel(0xffffffff, PMU_BASE_ADDR + PMU_NOC_AUTO_CON0);
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writel(0x000f000f, PMU_BASE_ADDR + PMU_NOC_AUTO_CON1);
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/* Disable eDP phy by default */
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writel(0x00070007, EDP_PHY_GRF_CON10);
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writel(0x0ff10ff1, EDP_PHY_GRF_CON0);
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/* Set core pvtpll ring length */
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writel(0x00ff002b, CPU_GRF_BASE + GRF_CORE_PVTPLL_CON0);
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/* Set the emmc sdmmc0 to secure */
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rk_clrreg(SGRF_BASE + SGRF_SOC_CON4, (EMMC_HPROT_SECURE_CTRL << 11
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| SDMMC0_HPROT_SECURE_CTRL << 4));
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/* set the emmc driver strength to level 2 */
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writel(0x3f3f0707, GRF_BASE + GRF_GPIO1B_DS_2);
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writel(0x3f3f0707, GRF_BASE + GRF_GPIO1B_DS_3);
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writel(0x3f3f0707, GRF_BASE + GRF_GPIO1C_DS_0);
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writel(0x3f3f0707, GRF_BASE + GRF_GPIO1C_DS_1);
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writel(0x3f3f0707, GRF_BASE + GRF_GPIO1C_DS_2);
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writel(0x3f3f0707, GRF_BASE + GRF_GPIO1C_DS_3);
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#endif
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return 0;
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}
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