mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-17 18:28:55 +00:00
5d7a95f499
Synchronise device trees with linux v5.19-rc5. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
304 lines
7 KiB
Text
304 lines
7 KiB
Text
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2016 PHYTEC Messtechnik GmbH
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* Author: Christian Hemp <c.hemp@phytec.de>
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*/
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/ {
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model = "PHYTEC phyBOARD-Segin i.MX6 UltraLite";
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compatible = "phytec,imx6ul-pbacd-10", "phytec,imx6ul-pcl063", "fsl,imx6ul";
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aliases {
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rtc0 = &i2c_rtc;
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rtc1 = &snvs_rtc;
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};
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reg_sound_1v8: regulator-1v8 {
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compatible = "regulator-fixed";
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regulator-name = "i2s-audio-1v8";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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status = "disabled";
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};
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reg_sound_3v3: regulator-3v3 {
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compatible = "regulator-fixed";
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regulator-name = "i2s-audio-3v3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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status = "disabled";
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};
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reg_can1_en: regulator-can1 {
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compatible = "regulator-fixed";
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pinctrl-names = "default";
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pinctrl-0 = <&princtrl_flexcan1_en>;
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regulator-name = "Can";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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status = "disabled";
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};
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reg_adc1_vref_3v3: regulator-vref-3v3 {
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compatible = "regulator-fixed";
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regulator-name = "vref-3v3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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};
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sound: sound {
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compatible = "simple-audio-card";
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simple-audio-card,name = "phyBOARD-Segin-TLV320AIC3007";
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simple-audio-card,format = "i2s";
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simple-audio-card,bitclock-master = <&dailink_master>;
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simple-audio-card,frame-master = <&dailink_master>;
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simple-audio-card,widgets =
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"Line", "Line In",
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"Line", "Line Out",
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"Speaker", "Speaker";
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simple-audio-card,routing =
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"Line Out", "LLOUT",
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"Line Out", "RLOUT",
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"Speaker", "SPOP",
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"Speaker", "SPOM",
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"LINE1L", "Line In",
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"LINE1R", "Line In";
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status = "disabled";
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simple-audio-card,cpu {
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sound-dai = <&sai2>;
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};
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dailink_master: simple-audio-card,codec {
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sound-dai = <&tlv320>;
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clocks = <&clks IMX6UL_CLK_SAI2>;
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};
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};
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};
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&adc1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_adc1>;
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vref-supply = <®_adc1_vref_3v3>;
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/*
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* driver can not separate a specific channel so we request 4 channels
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* here - we need only the fourth channel
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*/
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num-channels = <4>;
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status = "disabled";
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};
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&can1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_flexcan1>;
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xceiver-supply = <®_can1_en>;
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status = "disabled";
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};
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&clks {
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assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
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assigned-clock-rates = <786432000>;
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};
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&ecspi3 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_ecspi3>;
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cs-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>;
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status = "disabled";
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};
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&fec2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_enet2>;
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phy-mode = "rmii";
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phy-handle = <ðphy2>;
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status = "disabled";
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};
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&i2c1 {
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tlv320: codec@18 {
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compatible = "ti,tlv320aic3007";
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#sound-dai-cells = <0>;
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reg = <0x18>;
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AVDD-supply = <®_sound_3v3>;
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IOVDD-supply = <®_sound_3v3>;
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DRVDD-supply = <®_sound_3v3>;
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DVDD-supply = <®_sound_1v8>;
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status = "disabled";
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};
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i2c_rtc: rtc@68 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_rtc_int>;
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compatible = "microcrystal,rv4162";
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reg = <0x68>;
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interrupt-parent = <&gpio5>;
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interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
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status = "disabled";
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};
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};
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&mdio {
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ethphy2: ethernet-phy@2 {
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reg = <2>;
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micrel,led-mode = <1>;
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clocks = <&clks IMX6UL_CLK_ENET2_REF>;
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clock-names = "rmii-ref";
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status = "disabled";
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};
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};
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&sai2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_sai2>;
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assigned-clocks = <&clks IMX6UL_CLK_SAI2_SEL>,
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<&clks IMX6UL_CLK_SAI2>;
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assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
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assigned-clock-rates = <0>, <19200000>;
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fsl,sai-mclk-direction-output;
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status = "disabled";
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};
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&uart5 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart5>;
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uart-has-rtscts;
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status = "disabled";
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};
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&usbotg1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usb_otg1_id>;
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dr_mode = "otg";
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status = "disabled";
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};
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&usbotg2 {
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dr_mode = "host";
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disable-over-current;
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status = "disabled";
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};
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&usdhc1 {
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pinctrl-names = "default", "state_100mhz", "state_200mhz";
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pinctrl-0 = <&pinctrl_usdhc1>;
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pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
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pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
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cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
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no-1-8-v;
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keep-power-in-suspend;
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wakeup-source;
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disable-wp;
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status = "disabled";
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};
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&iomuxc {
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pinctrl_adc1: adc1grp {
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fsl,pins = <
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MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0
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>;
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};
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pinctrl_ecspi3: ecspi3grp {
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fsl,pins = <
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MX6UL_PAD_UART2_RTS_B__ECSPI3_MISO 0x10b0
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MX6UL_PAD_UART2_CTS_B__ECSPI3_MOSI 0x10b0
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MX6UL_PAD_UART2_RX_DATA__ECSPI3_SCLK 0x10b0
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MX6UL_PAD_UART2_TX_DATA__GPIO1_IO20 0x10b0
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>;
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};
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pinctrl_enet2: enet2grp {
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fsl,pins = <
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MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0
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MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0
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MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
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MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
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MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b010
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MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b010
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MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b010
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MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b010
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>;
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};
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pinctrl_flexcan1: flexcan1 {
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fsl,pins = <
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MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x0b0b0
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MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x0b0b0
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>;
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};
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princtrl_flexcan1_en: flexcan1engrp {
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fsl,pins = <
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MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x17059
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>;
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};
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pinctrl_rtc_int: rtcintgrp {
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fsl,pins = <
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MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x17059
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>;
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};
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pinctrl_sai2: sai2grp {
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fsl,pins = <
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MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088
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MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088
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MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x11088
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MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x11088
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MX6UL_PAD_JTAG_TMS__SAI2_MCLK 0x17088
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>;
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};
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pinctrl_uart5: uart5grp {
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fsl,pins = <
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MX6UL_PAD_UART5_TX_DATA__UART5_DCE_TX 0x1b0b1
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MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX 0x1b0b1
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MX6UL_PAD_GPIO1_IO08__UART5_DCE_RTS 0x1b0b1
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MX6UL_PAD_GPIO1_IO09__UART5_DCE_CTS 0x1b0b1
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>;
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};
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pinctrl_usb_otg1_id: usbotg1idgrp {
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fsl,pins = <
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MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059
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>;
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};
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pinctrl_usdhc1: usdhc1grp {
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fsl,pins = <
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MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
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MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059
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MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
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MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
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MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
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MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
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MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059
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>;
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};
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pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
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fsl,pins = <
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MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9
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MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9
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MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9
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MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
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MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
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MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9
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>;
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};
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pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
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fsl,pins = <
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MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9
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MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9
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MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9
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MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9
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MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9
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MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9
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>;
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};
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};
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