mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-16 17:58:23 +00:00
dd5b58c491
Perform a simple rename of CONFIG_MALLOC_F_ADDR to CFG_MALLOC_F_ADDR Signed-off-by: Tom Rini <trini@konsulko.com>
172 lines
4.6 KiB
C
172 lines
4.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright 2019 NXP
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* Copyright 2022 Linaro
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*/
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#ifndef __IMX8MP_RSB3720_H
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#define __IMX8MP_RSB3720_H
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#include <linux/sizes.h>
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#include <linux/stringify.h>
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#include <asm/arch/imx-regs.h>
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#include <config_distro_bootcmd.h>
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#define CFG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
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/* GUIDs for capsule updatable firmware images */
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#define IMX8MP_RSB3720A1_4G_FIT_IMAGE_GUID \
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EFI_GUID(0xb1251e89, 0x384a, 0x4635, 0xa8, 0x06, \
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0x3a, 0xa0, 0xb0, 0xe9, 0xf9, 0x65)
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#define IMX8MP_RSB3720A1_6G_FIT_IMAGE_GUID \
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EFI_GUID(0xb5fb6f08, 0xe142, 0x4db1, 0x97, 0xea, \
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0x5f, 0xd3, 0x6b, 0x9b, 0xe5, 0xb9)
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#ifdef CONFIG_SPL_BUILD
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#define CFG_MALLOC_F_ADDR 0x184000 /* malloc f used before \
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* GD_FLG_FULL_MALLOC_INIT \
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* set \
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*/
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#if defined(CONFIG_NAND_BOOT)
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#define CONFIG_SPL_NAND_MXS
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#endif
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#endif
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/* ENET Config */
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/* ENET1 */
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#if defined(CONFIG_CMD_NET)
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#define CFG_FEC_MXC_PHYADDR 4
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#define PHY_ANEG_TIMEOUT 20000
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#endif
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#if CONFIG_IS_ENABLED(CMD_MMC)
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# define BOOT_TARGET_MMC(func) \
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func(MMC, mmc, 2) \
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func(MMC, mmc, 1)
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#else
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# define BOOT_TARGET_MMC(func)
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#endif
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#if CONFIG_IS_ENABLED(CMD_PXE)
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# define BOOT_TARGET_PXE(func) func(PXE, pxe, na)
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#else
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# define BOOT_TARGET_PXE(func)
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#endif
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#if CONFIG_IS_ENABLED(CMD_DHCP)
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# define BOOT_TARGET_DHCP(func) func(DHCP, dhcp, na)
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#else
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# define BOOT_TARGET_DHCP(func)
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#endif
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#define BOOT_TARGET_DEVICES(func) \
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BOOT_TARGET_MMC(func) \
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BOOT_TARGET_PXE(func) \
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BOOT_TARGET_DHCP(func)
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/* Initial environment variables */
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#define CFG_EXTRA_ENV_SETTINGS \
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BOOTENV \
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"script=boot.scr\0" \
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"image=Image\0" \
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"splashimage=0x50000000\0" \
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"console=ttymxc2,115200 earlycon=ec_imx6q,0x30880000,115200\0" \
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"fdt_addr=0x43000000\0" \
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"fdt_addr_r=0x43000000\0" \
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"boot_fit=no\0" \
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"dfu_alt_info=mmc 2=flash-bin raw 0 0x1B00 mmcpart 1\0" \
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"fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
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"fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
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"initrd_addr=0x43800000\0" \
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"bootm_size=0x10000000\0" \
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"mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
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"mmcpart=1\0" \
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"mmcroot=/dev/mmcblk1p2 rootwait rw\0" \
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"mmcautodetect=yes\0" \
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"mmcargs=setenv bootargs ${jh_clk} console=${console} root=${mmcroot}\0 " \
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"loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
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"bootscript=echo Running bootscript from mmc ...; " \
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"source\0" \
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"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
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"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
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"kernel_addr_r=0x40480000\0" \
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"pxefile_addr_r=0x40480000\0" \
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"ramdisk_addr_r=0x43800000\0" \
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"mmcboot=echo Booting from mmc ...; " \
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"run mmcargs; " \
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"if test ${boot_fit} = yes || test ${boot_fit} = try; then " \
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"bootm ${loadaddr}; " \
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"else " \
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"if run loadfdt; then " \
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"booti ${loadaddr} - ${fdt_addr}; " \
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"else " \
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"echo WARN: Cannot load the DT; " \
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"fi; " \
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"fi;\0" \
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"netargs=setenv bootargs ${jh_clk} console=${console} " \
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"root=/dev/nfs " \
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"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
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"netboot=echo Booting from net ...; " \
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"run netargs; " \
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"if test ${ip_dyn} = yes; then " \
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"setenv get_cmd dhcp; " \
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"else " \
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"setenv get_cmd tftp; " \
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"fi; " \
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"${get_cmd} ${loadaddr} ${image}; " \
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"if test ${boot_fit} = yes || test ${boot_fit} = try; then " \
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"bootm ${loadaddr}; " \
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"else " \
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"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
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"booti ${loadaddr} - ${fdt_addr}; " \
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"else " \
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"echo WARN: Cannot load the DT; " \
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"fi; " \
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"fi;\0"
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/* Link Definitions */
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#define CFG_SYS_INIT_RAM_ADDR 0x40000000
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#define CFG_SYS_INIT_RAM_SIZE 0x80000
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/* Totally 6GB or 4G DDR */
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#define CFG_SYS_SDRAM_BASE 0x40000000
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#define PHYS_SDRAM 0x40000000
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#if defined(CONFIG_TARGET_IMX8MP_RSB3720A1_6G)
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#define PHYS_SDRAM_SIZE 0xC0000000 /* 3 GB */
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#define PHYS_SDRAM_2 0x100000000
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#define PHYS_SDRAM_2_SIZE 0xC0000000 /* 3 GB */
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#elif defined(CONFIG_TARGET_IMX8MP_RSB3720A1_4G)
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#define PHYS_SDRAM_SIZE 0x80000000 /* 2 GB */
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#define PHYS_SDRAM_2 0xC0000000
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#define PHYS_SDRAM_2_SIZE 0x80000000 /* 2 GB */
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#endif
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#define CONFIG_MXC_UART_BASE UART3_BASE_ADDR
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#define CFG_SYS_FSL_USDHC_NUM 2
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#define CFG_SYS_FSL_ESDHC_ADDR 0
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#ifdef CONFIG_FSL_FSPI
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#define FSL_FSPI_FLASH_SIZE SZ_32M
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#define FSL_FSPI_FLASH_NUM 1
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#define FSPI0_BASE_ADDR 0x30bb0000
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#define FSPI0_AMBA_BASE 0x0
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#define CONFIG_FSPI_QUAD_SUPPORT
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#define CONFIG_SYS_FSL_FSPI_AHB
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#endif
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#ifdef CONFIG_NAND_MXS
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/* NAND stuff */
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#define CFG_SYS_NAND_BASE 0x20000000
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#endif /* CONFIG_NAND_MXS */
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#endif /* __IMX8MP_RSB3720_H */
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