mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-16 16:23:14 +00:00
29caf9305b
Globally replace all occurances of WATCHDOG_RESET() with schedule(), which handles the HW_WATCHDOG functionality and the cyclic infrastructure. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Tom Rini <trini@konsulko.com> [am335x_evm, mx6cuboxi, rpi_3,dra7xx_evm, pine64_plus, am65x_evm, j721e_evm]
46 lines
1.1 KiB
C
46 lines
1.1 KiB
C
// SPDX-License-Identifier: GPL-2.0+
|
|
/*
|
|
* (C) Copyright 2002
|
|
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
|
*/
|
|
|
|
#include <common.h>
|
|
#include <cpu_func.h>
|
|
#include <asm/cache.h>
|
|
#include <watchdog.h>
|
|
|
|
static ulong maybe_watchdog_reset(ulong flushed)
|
|
{
|
|
flushed += CONFIG_SYS_CACHELINE_SIZE;
|
|
if (flushed >= CONFIG_CACHE_FLUSH_WATCHDOG_THRESHOLD) {
|
|
schedule();
|
|
flushed = 0;
|
|
}
|
|
return flushed;
|
|
}
|
|
|
|
void flush_cache(ulong start_addr, ulong size)
|
|
{
|
|
ulong addr, start, end;
|
|
ulong flushed = 0;
|
|
|
|
start = start_addr & ~(CONFIG_SYS_CACHELINE_SIZE - 1);
|
|
end = start_addr + size - 1;
|
|
|
|
for (addr = start; (addr <= end) && (addr >= start);
|
|
addr += CONFIG_SYS_CACHELINE_SIZE) {
|
|
asm volatile("dcbst 0,%0" : : "r" (addr) : "memory");
|
|
flushed = maybe_watchdog_reset(flushed);
|
|
}
|
|
/* wait for all dcbst to complete on bus */
|
|
asm volatile("sync" : : : "memory");
|
|
|
|
for (addr = start; (addr <= end) && (addr >= start);
|
|
addr += CONFIG_SYS_CACHELINE_SIZE) {
|
|
asm volatile("icbi 0,%0" : : "r" (addr) : "memory");
|
|
flushed = maybe_watchdog_reset(flushed);
|
|
}
|
|
asm volatile("sync" : : : "memory");
|
|
/* flush prefetch queue */
|
|
asm volatile("isync" : : : "memory");
|
|
}
|