mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-18 10:48:51 +00:00
4375598c52
Register r0 should be set to return value 0x0 - NO_ERR.
Set r0 with return value after all registers are restored from the
stack, so that the return value is always correct.
Signed-off-by: Pali Rohár <pali@kernel.org>
Fixes: 944c7a3176 ("arm: mvebu: Add option to use UART xmodem protocol via kwboot")
Reviewed-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Chris Packham <judge.packham@gmail.com>
Tested-by: Chris Packham <judge.packham@gmail.com>
70 lines
1.4 KiB
ArmAsm
70 lines
1.4 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0+ */
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#include <config.h>
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#include <linux/linkage.h>
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ENTRY(save_boot_params)
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stmfd sp!, {r0 - r12, lr} /* @ save registers on stack */
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ldr r12, =CONFIG_SPL_BOOTROM_SAVE
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str sp, [r12]
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b save_boot_params_ret
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ENDPROC(save_boot_params)
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ENTRY(return_to_bootrom)
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ldr r12, =CONFIG_SPL_BOOTROM_SAVE
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ldr sp, [r12]
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ldmfd sp!, {r0 - r12, lr} /* @ restore registers from stack */
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mov r0, #0x0 /* @ return value: 0x0 NO_ERR */
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bx lr /* @ return to bootrom */
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ENDPROC(return_to_bootrom)
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/*
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* cache_inv - invalidate Cache line
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* r0 - dest
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*/
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.global cache_inv
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.type cache_inv, %function
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cache_inv:
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stmfd sp!, {r1-r12}
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mcr p15, 0, r0, c7, c6, 1
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ldmfd sp!, {r1-r12}
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bx lr
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/*
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* flush_l1_v6 - l1 cache clean invalidate
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* r0 - dest
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*/
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.global flush_l1_v6
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.type flush_l1_v6, %function
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flush_l1_v6:
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stmfd sp!, {r1-r12}
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mcr p15, 0, r0, c7, c10, 5 /* @ data memory barrier */
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mcr p15, 0, r0, c7, c14, 1 /* @ clean & invalidate D line */
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mcr p15, 0, r0, c7, c10, 4 /* @ data sync barrier */
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ldmfd sp!, {r1-r12}
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bx lr
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/*
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* flush_l1_v7 - l1 cache clean invalidate
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* r0 - dest
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*/
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.global flush_l1_v7
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.type flush_l1_v7, %function
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flush_l1_v7:
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stmfd sp!, {r1-r12}
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dmb /* @data memory barrier */
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mcr p15, 0, r0, c7, c14, 1 /* @ clean & invalidate D line */
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dsb /* @data sync barrier */
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ldmfd sp!, {r1-r12}
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bx lr
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