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https://github.com/AsahiLinux/u-boot
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dd2ad2f131
The default configuration for QSPI AHB bus can't support 16MB+. But some flash on NXP layerscape board are more than 16MB. Signed-off-by: Yuan Yao <yao.yuan@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
150 lines
3.1 KiB
Text
150 lines
3.1 KiB
Text
config ARCH_LS1012A
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bool
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select FSL_LSCH2
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select SYS_FSL_DDR_BE
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select SYS_FSL_MMDC
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select SYS_FSL_ERRATUM_A010315
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config ARCH_LS1043A
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bool
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select FSL_LSCH2
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select SYS_FSL_DDR_BE
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select SYS_FSL_DDR_VER_50
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select SYS_FSL_ERRATUM_A010315
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select SYS_FSL_ERRATUM_A010539
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config ARCH_LS1046A
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bool
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select FSL_LSCH2
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select SYS_FSL_DDR_BE
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select SYS_FSL_DDR4
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select SYS_FSL_DDR_VER_50
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select SYS_FSL_ERRATUM_A010539
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select SYS_FSL_SRDS_2
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config ARCH_LS2080A
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bool
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select FSL_LSCH3
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select SYS_FSL_DDR4
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select SYS_FSL_DDR_LE
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select SYS_FSL_DDR_VER_50
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select SYS_FSL_HAS_DP_DDR
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select SYS_FSL_SRDS_2
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config FSL_LSCH2
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bool
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select SYS_FSL_SRDS_1
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select SYS_HAS_SERDES
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config FSL_LSCH3
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bool
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select SYS_FSL_SRDS_1
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select SYS_HAS_SERDES
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menu "Layerscape architecture"
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depends on FSL_LSCH2 || FSL_LSCH3
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config SYS_FSL_MMDC
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bool
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config SYS_FSL_ERRATUM_A010315
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bool "Workaround for PCIe erratum A010315"
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config SYS_FSL_ERRATUM_A010539
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bool "Workaround for PIN MUX erratum A010539"
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config MAX_CPUS
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int "Maximum number of CPUs permitted for Layerscape"
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default 4 if ARCH_LS1043A
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default 4 if ARCH_LS1046A
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default 16 if ARCH_LS2080A
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default 1
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help
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Set this number to the maximum number of possible CPUs in the SoC.
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SoCs may have multiple clusters with each cluster may have multiple
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ports. If some ports are reserved but higher ports are used for
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cores, count the reserved ports. This will allocate enough memory
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in spin table to properly handle all cores.
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config NUM_DDR_CONTROLLERS
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int "Maximum DDR controllers"
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default 3 if ARCH_LS2080A
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default 1
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config SECURE_BOOT
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bool
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help
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Enable Freescale Secure Boot feature
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config QSPI_AHB_INIT
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bool "Init the QSPI AHB bus"
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help
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The default setting for QSPI AHB bus just support 3bytes addressing.
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But some QSPI flash size up to 64MBytes, so initialize the QSPI AHB
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bus for those flashes to support the full QSPI flash size.
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config SYS_FSL_IFC_BANK_COUNT
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int "Maximum banks of Integrated flash controller"
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depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A
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default 4 if ARCH_LS1043A
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default 4 if ARCH_LS1046A
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default 8 if ARCH_LS2080A
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config SYS_FSL_HAS_DP_DDR
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bool
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config SYS_FSL_SRDS_1
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bool
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config SYS_FSL_SRDS_2
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bool
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config SYS_HAS_SERDES
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bool
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config SYS_FSL_DDR
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bool "Freescale DDR driver"
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help
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Select Freescale General DDR driver, shared between most Freescale
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PowerPC- based SoCs (such as mpc83xx, mpc85xx, mpc86xx) and ARM-
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based Layerscape SoCs (such as ls2080a).
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config SYS_FSL_DDR_BE
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bool
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help
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Access DDR registers in big-endian.
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config SYS_FSL_DDR_LE
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bool
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help
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Access DDR registers in little-endian.
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config SYS_FSL_DDR_VER
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int
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default 50 if SYS_FSL_DDR_VER_50
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config SYS_FSL_DDR_VER_50
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bool
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config SYS_FSL_DDRC_ARM_GEN3
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bool
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config SYS_FSL_DDRC_GEN4
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bool
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config SYS_FSL_DDR3
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bool "Freescale DDR3 controller"
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depends on !SYS_FSL_DDR4
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select SYS_FSL_DDR
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select SYS_FSL_DDRC_ARM_GEN3
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help
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Enable Freescale DDR3 controller on ARM-based SoCs.
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config SYS_FSL_DDR4
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bool "Freescale DDR4 controller"
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select SYS_FSL_DDR
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select SYS_FSL_DDRC_GEN4
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help
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Enable Freescale DDR4 controller.
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endmenu
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