mirror of
https://github.com/AsahiLinux/u-boot
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85e1f6be03
usdhc4 node need to update pinctrl, bus-width and non-removable properties, sync the same from Linux. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
236 lines
6.4 KiB
Text
236 lines
6.4 KiB
Text
/*
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* Copyright (C) 2015 Amarula Solutions B.V.
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*
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* This file is dual-licensed: you can use it either under the terms
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* of the GPL or the X11 license, at your option. Note that this dual
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* licensing only applies to this file, and not this project as a
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* whole.
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*
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* a) This file is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* version 2 as published by the Free Software Foundation.
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*
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* This file is distributed in the hope that it will be useful
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* Or, alternatively
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*
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* b) Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use
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* copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/clock/imx6qdl-clock.h>
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/ {
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aliases {
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mmc1 = &usdhc3;
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mmc2 = &usdhc4;
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};
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memory {
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reg = <0x10000000 0x80000000>;
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};
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};
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&fec {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_enet>;
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phy-handle = <ð_phy>;
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phy-mode = "rgmii";
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status = "okay";
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mdio {
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eth_phy: ethernet-phy {
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rxc-skew-ps = <1140>;
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txc-skew-ps = <1140>;
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txen-skew-ps = <600>;
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rxdv-skew-ps = <240>;
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rxd0-skew-ps = <420>;
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rxd1-skew-ps = <600>;
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rxd2-skew-ps = <420>;
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rxd3-skew-ps = <240>;
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txd0-skew-ps = <60>;
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txd1-skew-ps = <60>;
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txd2-skew-ps = <60>;
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txd3-skew-ps = <240>;
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};
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};
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};
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&i2c1 {
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clock-frequency = <100000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c1>;
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status = "okay";
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};
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&i2c2 {
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clock-frequency = <100000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c2>;
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status = "okay";
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};
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&i2c3 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c3>;
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status = "okay";
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};
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&uart4 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart4>;
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status = "okay";
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};
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&usdhc3 {
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u-boot,dm-spl;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usdhc3>;
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cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
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no-1-8-v;
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status = "okay";
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};
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&usdhc4 {
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u-boot,dm-spl;
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pinctrl-names = "default", "state_100mhz", "state_200mhz";
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pinctrl-0 = <&pinctrl_usdhc4>;
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pinctrl-1 = <&pinctrl_usdhc4_100mhz>;
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pinctrl-2 = <&pinctrl_usdhc4_200mhz>;
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bus-witdh = <8>;
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no-1-8-v;
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non-removable;
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status = "okay";
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};
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&iomuxc {
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pinctrl_enet: enetgrp {
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fsl,pins = <
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MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
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MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
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MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
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MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
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MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
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MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
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MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
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MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
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MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
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MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
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MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
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MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
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MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
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MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
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MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
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MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
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>;
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};
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pinctrl_i2c1: i2c1grp {
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fsl,pins = <
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MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
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MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
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>;
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};
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pinctrl_i2c2: i2c2grp {
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fsl,pins = <
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MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
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MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
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>;
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};
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pinctrl_i2c3: i2c3grp {
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fsl,pins = <
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MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1
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MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
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>;
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};
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pinctrl_uart4: uart4grp {
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fsl,pins = <
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MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
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MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
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>;
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};
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pinctrl_usdhc3: usdhc3grp {
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u-boot,dm-spl;
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fsl,pins = <
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MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17070
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MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10070
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MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17070
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MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17070
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MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17070
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MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17070
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>;
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};
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pinctrl_usdhc4: usdhc4grp {
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u-boot,dm-spl;
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fsl,pins = <
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MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17070
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MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10070
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MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17070
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MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17070
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MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17070
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MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17070
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MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17070
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MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17070
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MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17070
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MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17070
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>;
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};
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pinctrl_usdhc4_100mhz: usdhc4grp_100mhz {
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fsl,pins = <
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MX6QDL_PAD_SD4_CMD__SD4_CMD 0x170B1
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MX6QDL_PAD_SD4_CLK__SD4_CLK 0x100B1
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MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x170B1
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MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x170B1
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MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x170B1
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MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x170B1
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MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x170B1
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MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x170B1
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MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x170B1
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MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x170B1
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>;
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};
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pinctrl_usdhc4_200mhz: usdhc4grp_200mhz {
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fsl,pins = <
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MX6QDL_PAD_SD4_CMD__SD4_CMD 0x170F9
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MX6QDL_PAD_SD4_CLK__SD4_CLK 0x100F9
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MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x170F9
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MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x170F9
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MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x170F9
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MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x170F9
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MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x170F9
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MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x170F9
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MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x170F9
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MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x170F9
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>;
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};
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};
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