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dd1033e4e0
This family of SoCs are found in the Microsemi Switches solution and have already a support in the linux kernel. Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
30 lines
741 B
C
30 lines
741 B
C
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2018 Microsemi Corporation
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*/
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#include <common.h>
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#include <asm/sections.h>
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#include <asm/io.h>
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#include <asm/reboot.h>
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void _machine_restart(void)
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{
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register u32 resetbits = PERF_SOFT_RST_SOFT_CHIP_RST;
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(void)readl(BASE_DEVCPU_GCB + PERF_SOFT_RST);
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/* Make sure VCore is NOT protected from reset */
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clrbits_le32(BASE_CFG + ICPU_RESET, ICPU_RESET_CORE_RST_PROTECT);
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/* Change to SPI bitbang for SPI reset workaround... */
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writel(ICPU_SW_MODE_SW_SPI_CS_OE(1) | ICPU_SW_MODE_SW_SPI_CS(1) |
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ICPU_SW_MODE_SW_PIN_CTRL_MODE, BASE_CFG + ICPU_SW_MODE);
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/* Do the global reset */
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writel(resetbits, BASE_DEVCPU_GCB + PERF_SOFT_RST);
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while (1)
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; /* NOP */
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}
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