mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-13 14:53:06 +00:00
067716bac5
This series moves the CONFIG_SYS_CACHELINE_SIZE. First, in nearly all cases we are mirroring the values used by the Linux Kernel here. Also, so long as (and in this case, it is true) we implement flushes in hunks that are no larger than the smallest implementation (and given that we mirror the Linux Kernel, again we are fine) it is OK to align higher. The biggest changes here are that we always use 64 bytes for CPU_V7 even if for example the underlying core is only 32 bytes (this mirrors Linux). Second, we say ARM64 uses 64 bytes not 128 (as found in the Linux Kernel) as we do not need multi-platform support (to this degree) and only the Cavium ThunderX 88xx series has a use for such large alignment. Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Prafulla Wadaskar <prafulla@marvell.com> Cc: Luka Perkov <luka.perkov@sartura.hr> Cc: Stefan Roese <sr@denx.de> Cc: Nagendra T S <nagendra@mistralsolutions.com> Cc: Vaibhav Hiremath <hvaibhav@ti.com> Acked-by: Lokesh Vutla <lokeshvutla@ti.com> Cc: Steve Rae <steve.rae@raedomain.com> Cc: Igor Grinberg <grinberg@compulab.co.il> Cc: Nikita Kiryanov <nikita@compulab.co.il> Cc: Stefan Agner <stefan.agner@toradex.com> Acked-by: Heiko Schocher <hs@denx.de> Cc: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> Cc: Peter Griffin <peter.griffin@linaro.org> Acked-by: Paul Kocialkowski <contact@paulk.fr> Cc: Anatolij Gustschin <agust@denx.de> Acked-by: "Pali Rohár" <pali.rohar@gmail.com> Cc: Adam Ford <aford173@gmail.com> Cc: Steve Sakoman <sakoman@gmail.com> Cc: Grazvydas Ignotas <notasas@gmail.com> Cc: Nishanth Menon <nm@ti.com> Cc: Stephen Warren <swarren@wwwdotorg.org> Cc: Robert Baldyga <r.baldyga@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Thomas Weber <weber@corscience.de> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: David Feng <fenghua@phytium.com.cn> Cc: Alison Wang <b18965@freescale.com> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Simon Glass <sjg@chromium.org> Cc: York Sun <york.sun@nxp.com> Cc: Shengzhou Liu <Shengzhou.Liu@nxp.com> Cc: Mingkai Hu <mingkai.hu@nxp.com> Cc: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Cc: Aneesh Bansal <aneesh.bansal@freescale.com> Cc: Saksham Jain <saksham.jain@nxp.com> Cc: Qianyu Gong <qianyu.gong@nxp.com> Cc: Wang Dongsheng <dongsheng.wang@nxp.com> Cc: Alex Porosanu <alexandru.porosanu@freescale.com> Cc: Hongbo Zhang <hongbo.zhang@nxp.com> Cc: tang yuantian <Yuantian.Tang@freescale.com> Cc: Rajesh Bhagat <rajesh.bhagat@nxp.com> Cc: Josh Wu <josh.wu@atmel.com> Cc: Bo Shen <voice.shen@atmel.com> Cc: Viresh Kumar <viresh.kumar@linaro.org> Cc: Hannes Schmelzer <oe5hpm@oevsv.at> Cc: Thomas Chou <thomas@wytron.com.tw> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Sam Protsenko <semen.protsenko@linaro.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Christophe Ricard <christophe-h.ricard@st.com> Cc: Anand Moon <linux.amoon@gmail.com> Cc: Beniamino Galvani <b.galvani@gmail.com> Cc: Carlo Caione <carlo@endlessm.com> Cc: huang lin <hl@rock-chips.com> Cc: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Cc: Xu Ziyuan <xzy.xu@rock-chips.com> Cc: "jk.kernel@gmail.com" <jk.kernel@gmail.com> Cc: "Ariel D'Alessandro" <ariel@vanguardiasur.com.ar> Cc: Kever Yang <kever.yang@rock-chips.com> Cc: Samuel Egli <samuel.egli@siemens.com> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Hans de Goede <hdegoede@redhat.com> Cc: Ian Campbell <ijc@hellion.org.uk> Cc: Siarhei Siamashka <siarhei.siamashka@gmail.com> Cc: Boris Brezillon <boris.brezillon@free-electrons.com> Cc: Andre Przywara <andre.przywara@arm.com> Cc: Bernhard Nortmann <bernhard.nortmann@web.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Ben Whitten <ben.whitten@gmail.com> Cc: Tom Warren <twarren@nvidia.com> Cc: Alexander Graf <agraf@suse.de> Cc: Sekhar Nori <nsekhar@ti.com> Cc: Vitaly Andrianov <vitalya@ti.com> Cc: "Andrew F. Davis" <afd@ti.com> Cc: Murali Karicheri <m-karicheri2@ti.com> Cc: Carlos Hernandez <ceh@ti.com> Cc: Ladislav Michl <ladis@linux-mips.org> Cc: Ash Charles <ashcharles@gmail.com> Cc: Mugunthan V N <mugunthanvnm@ti.com> Cc: Daniel Allred <d-allred@ti.com> Cc: Gong Qianyu <Qianyu.Gong@freescale.com> Signed-off-by: Tom Rini <trini@konsulko.com> Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Chin Liang See <clsee@altera.com> Tested-by: Stephen Warren <swarren@nvidia.com> Acked-by: Paul Kocialkowski <contact@paulk.fr>
208 lines
6 KiB
C
208 lines
6 KiB
C
/*
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* (C) Copyright 2009 Samsung Electronics
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* Minkyu Kang <mk7.kang@samsung.com>
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* HeungJun Kim <riverful.kim@samsung.com>
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* Inki Dae <inki.dae@samsung.com>
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*
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* Configuation settings for the SAMSUNG SMDKC100 board.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* High Level Configuration Options
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* (easy to change)
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*/
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#define CONFIG_SAMSUNG 1 /* in a SAMSUNG core */
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#define CONFIG_S5P 1 /* which is in a S5P Family */
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#define CONFIG_S5PC100 1 /* which is in a S5PC100 */
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#define CONFIG_SMDKC100 1 /* working with SMDKC100 */
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#include <asm/arch/cpu.h> /* get chip and board defs */
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#define CONFIG_ARCH_CPU_INIT
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#define CONFIG_DISPLAY_CPUINFO
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#define CONFIG_DISPLAY_BOARDINFO
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/* input clock of PLL: SMDKC100 has 12MHz input clock */
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#define CONFIG_SYS_CLK_FREQ 12000000
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/* DRAM Base */
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#define CONFIG_SYS_SDRAM_BASE 0x30000000
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/* Text Base */
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#define CONFIG_SYS_TEXT_BASE 0x34800000
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#define CONFIG_SETUP_MEMORY_TAGS
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#define CONFIG_CMDLINE_TAG
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#define CONFIG_INITRD_TAG
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#define CONFIG_CMDLINE_EDITING
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/*
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* Size of malloc() pool
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* 1MB = 0x100000, 0x100000 = 1024 * 1024
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*/
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#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (1 << 20))
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/*
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* select serial console configuration
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*/
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#define CONFIG_SERIAL0 1 /* use SERIAL 0 on SMDKC100 */
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/* PWM */
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#define CONFIG_PWM 1
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/* allow to overwrite serial and ethaddr */
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_BAUDRATE 115200
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/***********************************************************
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* Command definition
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***********************************************************/
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#undef CONFIG_CMD_NAND
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#define CONFIG_CMD_REGINFO
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#define CONFIG_CMD_ONENAND
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#define CONFIG_CMD_MTDPARTS
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#define CONFIG_MTD_DEVICE
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#define CONFIG_MTD_PARTITIONS
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#define MTDIDS_DEFAULT "onenand0=s3c-onenand"
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#define MTDPARTS_DEFAULT "mtdparts=s3c-onenand:256k(bootloader)"\
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",128k@0x40000(params)"\
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",3m@0x60000(kernel)"\
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",16m@0x360000(test)"\
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",-(UBI)"
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#define NORMAL_MTDPARTS_DEFAULT MTDPARTS_DEFAULT
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#define CONFIG_BOOTCOMMAND "run ubifsboot"
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#define CONFIG_RAMDISK_BOOT "root=/dev/ram0 rw rootfstype=ext2" \
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" console=ttySAC0,115200n8" \
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" mem=128M"
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#define CONFIG_COMMON_BOOT "console=ttySAC0,115200n8" \
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" mem=128M " \
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" " MTDPARTS_DEFAULT
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#define CONFIG_BOOTARGS "root=/dev/mtdblock5 ubi.mtd=4" \
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" rootfstype=cramfs " CONFIG_COMMON_BOOT
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#define CONFIG_UPDATEB "updateb=onenand erase 0x0 0x40000;" \
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" onenand write 0x32008000 0x0 0x40000\0"
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_EXTRA_ENV_SETTINGS \
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CONFIG_UPDATEB \
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"updatek=" \
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"onenand erase 0x60000 0x300000;" \
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"onenand write 0x31008000 0x60000 0x300000\0" \
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"updateu=" \
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"onenand erase block 147-4095;" \
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"onenand write 0x32000000 0x1260000 0x8C0000\0" \
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"bootk=" \
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"onenand read 0x30007FC0 0x60000 0x300000;" \
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"bootm 0x30007FC0\0" \
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"flashboot=" \
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"set bootargs root=/dev/mtdblock${bootblock} " \
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"rootfstype=${rootfstype} " \
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"ubi.mtd=${ubiblock} ${opts} " CONFIG_COMMON_BOOT ";" \
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"run bootk\0" \
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"ubifsboot=" \
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"set bootargs root=ubi0!rootfs rootfstype=ubifs " \
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" ubi.mtd=${ubiblock} ${opts} " CONFIG_COMMON_BOOT "; " \
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"run bootk\0" \
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"boottrace=setenv opts initcall_debug; run bootcmd\0" \
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"android=" \
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"set bootargs root=ubi0!ramdisk ubi.mtd=${ubiblock} " \
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"rootfstype=ubifs init=/init.sh " CONFIG_COMMON_BOOT "; " \
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"run bootk\0" \
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"nfsboot=" \
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"set bootargs root=/dev/nfs ubi.mtd=${ubiblock} " \
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"nfsroot=${nfsroot},nolock " \
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"ip=${ipaddr}:${serverip}:${gatewayip}:" \
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"${netmask}:nowplus:usb0:off " CONFIG_COMMON_BOOT "; " \
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"run bootk\0" \
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"ramboot=" \
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"set bootargs " CONFIG_RAMDISK_BOOT \
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" initrd=0x33000000,8M ramdisk=8192\0" \
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"rootfstype=cramfs\0" \
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"mtdparts=" MTDPARTS_DEFAULT "\0" \
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"meminfo=mem=128M\0" \
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"nfsroot=/nfsroot/arm\0" \
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"bootblock=5\0" \
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"ubiblock=4\0" \
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"ubi=enabled"
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/*
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* Miscellaneous configurable options
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*/
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#define CONFIG_SYS_LONGHELP /* undef to save memory */
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#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
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#define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */
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#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
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/* Boot Argument Buffer Size */
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
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/* memtest works on */
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#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
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#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5e00000)
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#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE
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/* SMDKC100 has 1 banks of DRAM, we use only one in U-Boot */
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#define CONFIG_NR_DRAM_BANKS 1
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#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE /* SDRAM Bank #1 */
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#define PHYS_SDRAM_1_SIZE (128 << 20) /* 0x8000000, 128 MB Bank #1 */
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#define CONFIG_SYS_MONITOR_BASE 0x00000000
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/*-----------------------------------------------------------------------
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* FLASH and environment organization
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*/
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#define CONFIG_SYS_NO_FLASH 1
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#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* 256 KiB */
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#define CONFIG_IDENT_STRING " for SMDKC100"
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#if !defined(CONFIG_NAND_SPL) && (CONFIG_SYS_TEXT_BASE >= 0xc0000000)
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#define CONFIG_ENABLE_MMU
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#endif
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#ifdef CONFIG_ENABLE_MMU
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#define CONFIG_SYS_MAPPED_RAM_BASE 0xc0000000
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#else
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#define CONFIG_SYS_MAPPED_RAM_BASE CONFIG_SYS_SDRAM_BASE
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#endif
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/*-----------------------------------------------------------------------
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* Boot configuration
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*/
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#define CONFIG_ENV_IS_IN_ONENAND 1
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#define CONFIG_ENV_SIZE (128 << 10) /* 128KiB, 0x20000 */
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#define CONFIG_ENV_ADDR (256 << 10) /* 256KiB, 0x40000 */
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#define CONFIG_ENV_OFFSET (256 << 10) /* 256KiB, 0x40000 */
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#define CONFIG_USE_ONENAND_BOARD_INIT
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#define CONFIG_SAMSUNG_ONENAND 1
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#define CONFIG_SYS_ONENAND_BASE 0xE7100000
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#define CONFIG_DOS_PARTITION 1
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#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR - 0x1000000)
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/*
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* Ethernet Contoller driver
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*/
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#ifdef CONFIG_CMD_NET
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#define CONFIG_SMC911X 1 /* we have a SMC9115 on-board */
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#define CONFIG_SMC911X_16_BIT 1 /* SMC911X_16_BIT Mode */
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#define CONFIG_SMC911X_BASE 0x98800300 /* SMC911X Drive Base */
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#define CONFIG_ENV_SROM_BANK 3 /* Select SROM Bank-3 for Ethernet*/
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#endif /* CONFIG_CMD_NET */
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#endif /* __CONFIG_H */
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