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2fccd2d96b
This is an implementation of GPIOs for Tegra that uses driver model. It has been tested on trimslice and also using the new iotrace feature. The implementation uses a top-level GPIO device (which has no actual GPIOS). Under this all the banks are created as separate GPIO devices. The GPIOs are named as per the Tegra datasheet/header files: A0..A7, B0..B7, ..., Z0..Z7, AA0..AA7, etc. Since driver model is not yet available before relocation, or in SPL, a special function is provided for seaboard's SPL code. Signed-off-by: Simon Glass <sjg@chromium.org>
50 lines
1.2 KiB
C
50 lines
1.2 KiB
C
/*
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* (C) Copyright 2010,2011
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* NVIDIA Corporation <www.nvidia.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/tegra.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/funcmux.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/pinmux.h>
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#include <asm/gpio.h>
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/* TODO: Remove this code when the SPI switch is working */
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#if (CONFIG_MACH_TYPE != MACH_TYPE_VENTANA)
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void gpio_early_init_uart(void)
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{
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/* Enable UART via GPIO_PI3 (port 8, bit 3) so serial console works */
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#ifndef CONFIG_SPL_BUILD
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gpio_request(GPIO_PI3, NULL);
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#endif
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tegra_spl_gpio_direction_output(GPIO_PI3, 0);
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}
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#endif
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#ifdef CONFIG_TEGRA_MMC
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/*
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* Routine: pin_mux_mmc
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* Description: setup the pin muxes/tristate values for the SDMMC(s)
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*/
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void pin_mux_mmc(void)
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{
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funcmux_select(PERIPH_ID_SDMMC4, FUNCMUX_SDMMC4_ATB_GMA_GME_8_BIT);
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funcmux_select(PERIPH_ID_SDMMC3, FUNCMUX_SDMMC3_SDB_4BIT);
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/* For power GPIO PI6 */
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pinmux_tristate_disable(PMUX_PINGRP_ATA);
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/* For CD GPIO PI5 */
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pinmux_tristate_disable(PMUX_PINGRP_ATC);
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}
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#endif
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void pin_mux_usb(void)
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{
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/* For USB's GPIO PD0. For now, since we have no pinmux in fdt */
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pinmux_tristate_disable(PMUX_PINGRP_SLXK);
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}
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