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eab40f819d
The QONG module can be downsized and delivered with 128MB instead of 256MB. The patch adds run time support for the two different memory configurations. Signed-off-by: Stefano Babic <sbabic@denx.de>
236 lines
5.3 KiB
ArmAsm
236 lines
5.3 KiB
ArmAsm
/*
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* Copyright (C) 2009, Emcraft Systems, Ilya Yanok <yanok@emcraft.com>
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*
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* Based on board/freescale/mx31ads/lowlevel_init.S
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* by Guennadi Liakhovetski.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <asm/arch/mx31-regs.h>
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.macro REG reg, val
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ldr r2, =\reg
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ldr r3, =\val
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str r3, [r2]
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.endm
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.macro REG8 reg, val
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ldr r2, =\reg
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ldr r3, =\val
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strb r3, [r2]
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.endm
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.macro DELAY loops
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ldr r2, =\loops
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1:
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subs r2, r2, #1
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nop
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bcs 1b
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.endm
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.macro SETUP_RAM cfg, ctl
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/* B8xxxxxx - NAND, 8xxxxxxx - CSD0 RAM */
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REG 0xB8001010, 0x00000004
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ldr r3, =\cfg
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ldr r2, =WEIM_ESDCFG0
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str r3, [r2]
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REG 0xB8001000, 0x92100000
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REG 0x80000f00, 0x12344321
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REG 0xB8001000, 0xa2100000
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REG 0x80000000, 0x12344321
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REG 0x80000000, 0x12344321
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REG 0xB8001000, 0xb2100000
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REG8 0x80000033, 0xda
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REG8 0x81000000, 0xff
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ldr r3, =\ctl
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ldr r2, =WEIM_ESDCTL0
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str r3, [r2]
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REG 0x80000000, 0xDEADBEEF
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REG 0xB8001010, 0x0000000c
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.endm
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/* RedBoot: To support 133MHz DDR */
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.macro init_drive_strength
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/*
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* Disable maximum drive strength SDRAM/DDR lines by clearing DSE1 bits
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* in SW_PAD_CTL registers
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*/
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/* SDCLK */
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ldr r1, =IOMUXC_SW_PAD_CTL(0x2b)
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ldr r0, [r1, #0x6C]
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bic r0, r0, #(1 << 12)
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str r0, [r1, #0x6C]
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/* CAS */
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ldr r0, [r1, #0x70]
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bic r0, r0, #(1 << 22)
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str r0, [r1, #0x70]
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/* RAS */
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ldr r0, [r1, #0x74]
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bic r0, r0, #(1 << 2)
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str r0, [r1, #0x74]
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/* CS2 (CSD0) */
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ldr r0, [r1, #0x7C]
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bic r0, r0, #(1 << 22)
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str r0, [r1, #0x7C]
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/* DQM3 */
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ldr r0, [r1, #0x84]
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bic r0, r0, #(1 << 22)
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str r0, [r1, #0x84]
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/* DQM2, DQM1, DQM0, SD31-SD0, A25-A0, MA10 (0x288..0x2DC) */
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ldr r2, =22 /* (0x2E0 - 0x288) / 4 = 22 */
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pad_loop:
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ldr r0, [r1, #0x88]
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bic r0, r0, #(1 << 22)
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bic r0, r0, #(1 << 12)
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bic r0, r0, #(1 << 2)
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str r0, [r1, #0x88]
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add r1, r1, #4
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subs r2, r2, #0x1
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bne pad_loop
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.endm /* init_drive_strength */
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.globl lowlevel_init
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lowlevel_init:
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init_drive_strength
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/* Image Processing Unit: */
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/* Too early to switch display on? */
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/* Switch on Display Interface */
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REG IPU_CONF, IPU_CONF_DI_EN
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/* Clock Control Module: */
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REG CCM_CCMR, 0x074B0BF5 /* Use CKIH, MCU PLL off */
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DELAY 0x40000
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REG CCM_CCMR, 0x074B0BF5 | CCMR_MPE /* MCU PLL on */
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/* Switch to MCU PLL */
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REG CCM_CCMR, (0x074B0BF5 | CCMR_MPE) & ~CCMR_MDS
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/* 399-133-66.5 */
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ldr r0, =CCM_BASE
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ldr r1, =0xFF871650
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/* PDR0 */
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str r1, [r0, #0x4]
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ldr r1, MPCTL_PARAM_399
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/* MPCTL */
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str r1, [r0, #0x10]
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/* Set UPLL=240MHz, USB=60MHz */
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ldr r1, =0x49FCFE7F
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/* PDR1 */
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str r1, [r0, #0x8]
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ldr r1, UPCTL_PARAM_240
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/* UPCTL */
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str r1, [r0, #0x14]
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/* default CLKO to 1/8 of the ARM core */
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mov r1, #0x00000208
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/* COSR */
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str r1, [r0, #0x1c]
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/* Default: 1, 4, 12, 1 */
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REG CCM_SPCTL, PLL_PD(1) | PLL_MFD(4) | PLL_MFI(12) | PLL_MFN(1)
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check_ddr_module:
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/* Set stackpointer in internal RAM to call get_ram_size */
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ldr sp, =(IRAM_BASE_ADDR + IRAM_SIZE - 16)
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stmfd sp!, {r0-r11, ip, lr}
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mov ip, lr /* save link reg across call */
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ldr r0,=0x08000000
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SETUP_RAM ESDCFG0_256MB, ESDCTL0_256MB
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ldr r0,=0x80000000
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ldr r1,=0x10000000
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bl get_ram_size
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ldr r1,=0x10000000
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cmp r0,r1
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beq restore_regs
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SETUP_RAM ESDCFG0_128MB, ESDCTL0_128MB
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ldr r0,=0x80000000
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ldr r1,=0x08000000
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bl get_ram_size
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ldr r1,=0x08000000
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cmp r0,r1
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beq restore_regs
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restore_regs:
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ldmfd sp!, {r0-r11, ip, lr}
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mov lr, ip /* restore link reg */
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mov pc, lr
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MPCTL_PARAM_399:
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.word (((1 - 1) << 26) + ((52 - 1) << 16) + (7 << 10) + (35 << 0))
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UPCTL_PARAM_240:
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.word (((2 - 1) << 26) + ((13 - 1) << 16) + (9 << 10) + (3 << 0))
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.equ ESDCFG0_128MB, \
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(0 << 21) + /* tXP */ \
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(1 << 20) + /* tWTR */ \
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(2 << 18) + /* tRP */ \
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(1 << 16) + /* tMRD */ \
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(0 << 15) + /* tWR */ \
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(5 << 12) + /* tRAS */ \
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(1 << 10) + /* tRRD */ \
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(3 << 8) + /* tCAS */ \
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(2 << 4) + /* tRCD */ \
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(0x0F << 0) /* tRC */
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.equ ESDCTL0_128MB, \
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(1 << 31) + /* enable */ \
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(0 << 28) + /* mode */ \
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(0 << 27) + /* supervisor protect */ \
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(2 << 24) + /* 13 rows */ \
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(2 << 20) + /* 10 cols */ \
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(2 << 16) + /* 32 bit */ \
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(3 << 13) + /* 7.81us (64ms/8192) */ \
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(0 << 10) + /* power down timer */ \
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(0 << 8) + /* full page */ \
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(1 << 7) + /* burst length */ \
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(0 << 0) /* precharge timer */
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.equ ESDCFG0_256MB, \
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(3 << 21) + /* tXP */ \
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(0 << 20) + /* tWTR */ \
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(2 << 18) + /* tRP */ \
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(1 << 16) + /* tMRD */ \
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(0 << 15) + /* tWR */ \
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(5 << 12) + /* tRAS */ \
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(1 << 10) + /* tRRD */ \
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(3 << 8) + /* tCAS */ \
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(2 << 4) + /* tRCD */ \
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(7 << 0) /* tRC */
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.equ ESDCTL0_256MB, \
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(1 << 31) + \
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(0 << 28) + \
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(0 << 27) + \
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(3 << 24) + /* 14 rows */ \
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(2 << 20) + /* 10 cols */ \
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(2 << 16) + \
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(4 << 13) + /* 3.91us (64ms/16384) */ \
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(0 << 10) + \
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(0 << 8) + \
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(1 << 7) + \
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(0 << 0)
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