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https://github.com/AsahiLinux/u-boot
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1918ff5c95
This driver provides clock and reset control for the Renesas R9A07G044L
(RZ/G2L) and R9A07G044C (RZ/G2LC) SoC. It consists of two parts:
* driver code which is applicable to all SoCs in the RZ/G2L family.
* static data describing the clocks and resets which are specific to the
R9A07G044{L,C} SoCs. The identifier r9a07g044 (without a final letter)
is used to indicate that both SoCs are supported.
clk_set_rate() and clk_get_rate() are implemented only for the clocks
that are actually used in u-boot.
The CPG driver is marked with DM_FLAG_PRE_RELOC to ensure that its bind
function is called before the SCIF (serial port) driver is probed. This
is required so that we can de-assert the relevant reset signal during
the serial driver probe function.
This patch is based on the corresponding Linux v6.5 driver
(commit 52e12027d50affbf60c6c9c64db8017391b0c22e).
Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
27 lines
1.3 KiB
Makefile
27 lines
1.3 KiB
Makefile
obj-$(CONFIG_CLK_RCAR) += renesas-cpg-mssr.o
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obj-$(CONFIG_CLK_RCAR_CPG_LIB) += rcar-cpg-lib.o
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obj-$(CONFIG_CLK_RCAR_GEN2) += clk-rcar-gen2.o
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obj-$(CONFIG_CLK_R8A774A1) += r8a774a1-cpg-mssr.o
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obj-$(CONFIG_CLK_R8A774B1) += r8a774b1-cpg-mssr.o
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obj-$(CONFIG_CLK_R8A774C0) += r8a774c0-cpg-mssr.o
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obj-$(CONFIG_CLK_R8A774E1) += r8a774e1-cpg-mssr.o
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obj-$(CONFIG_CLK_R8A7790) += r8a7790-cpg-mssr.o
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obj-$(CONFIG_CLK_R8A7791) += r8a7791-cpg-mssr.o
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obj-$(CONFIG_CLK_R8A7792) += r8a7792-cpg-mssr.o
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obj-$(CONFIG_CLK_R8A7793) += r8a7791-cpg-mssr.o
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obj-$(CONFIG_CLK_R8A7794) += r8a7794-cpg-mssr.o
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obj-$(CONFIG_CLK_RCAR_GEN3) += clk-rcar-gen3.o
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obj-$(CONFIG_CLK_R8A7795) += r8a7795-cpg-mssr.o
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obj-$(CONFIG_CLK_R8A77960) += r8a7796-cpg-mssr.o
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obj-$(CONFIG_CLK_R8A77961) += r8a7796-cpg-mssr.o
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obj-$(CONFIG_CLK_R8A77965) += r8a77965-cpg-mssr.o
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obj-$(CONFIG_CLK_R8A77970) += r8a77970-cpg-mssr.o
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obj-$(CONFIG_CLK_R8A77980) += r8a77980-cpg-mssr.o
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obj-$(CONFIG_CLK_R8A77990) += r8a77990-cpg-mssr.o
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obj-$(CONFIG_CLK_R8A77995) += r8a77995-cpg-mssr.o
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obj-$(CONFIG_CLK_R8A779A0) += r8a779a0-cpg-mssr.o
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obj-$(CONFIG_CLK_R8A779F0) += r8a779f0-cpg-mssr.o
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obj-$(CONFIG_CLK_R8A779G0) += r8a779g0-cpg-mssr.o
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obj-$(CONFIG_CLK_R9A06G032) += r9a06g032-clocks.o
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obj-$(CONFIG_CLK_RZG2L) += rzg2l-cpg.o
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obj-$(CONFIG_CLK_R9A07G044) += r9a07g044-cpg.o
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