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d40ddae4b3
Define CONFIG_MPC85xx in arch/powerpc/cpu/mpc85xx/config.mk because all target boards with mpc85xx cpu define it. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
451 lines
14 KiB
C
451 lines
14 KiB
C
/*
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* (C) Copyright 2005 Embedded Alley Solutions, Inc.
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* Dan Malek <dan@embeddedalley.com>
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* Copied from STx GP3.
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* Updates for Silicon Tx GP3 SSA board.
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*
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* (C) Copyright 2002,2003 Motorola,Inc.
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* Xianghua Xiao <X.Xiao@motorola.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/* mpc8560ads board configuration file */
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/* please refer to doc/README.mpc85xx for more info */
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/* make sure you change the MAC address and other network params first,
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* search for CONFIG_ETHADDR,CONFIG_SERVERIP,etc in this file
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/* High Level Configuration Options */
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#define CONFIG_BOOKE 1 /* BOOKE */
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#define CONFIG_E500 1 /* BOOKE e500 family */
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#define CONFIG_CPM2 1 /* has CPM2 */
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#define CONFIG_STXSSA 1 /* Silicon Tx GPPP SSA board specific*/
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#define CONFIG_MPC8560 1
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#define CONFIG_SYS_TEXT_BASE 0xFFF80000
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#define CONFIG_PCI /* PCI ethernet support */
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#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
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#define CONFIG_TSEC_ENET /* tsec ethernet support*/
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#undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
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/* sysclk for MPC85xx
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*/
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#define CONFIG_SYS_CLK_FREQ 33000000 /* most pci cards are 33Mhz */
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/* Blinkin' LEDs for Robert :-)
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*/
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#define CONFIG_SHOW_ACTIVITY 1
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/*
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* These can be toggled for performance analysis, otherwise use default.
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*/
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#define CONFIG_L2_CACHE /* toggle L2 cache */
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#define CONFIG_BTB /* toggle branch predition */
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#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
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#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
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#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */
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#define CONFIG_SYS_MEMTEST_END 0x00400000
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/* Localbus connector. There are many options that can be
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* connected here, including sdram or lots of flash.
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* This address, however, is used to configure a 256M local bus
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* window that includes the Config latch below.
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*/
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#define CONFIG_SYS_LBC_OPTION_BASE 0xF0000000 /* Localbus Extension */
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#define CONFIG_SYS_LBC_OPTION_SIZE 256 /* 256MB */
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/* There are various flash options used, we configure for the largest,
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* which is 64Mbytes. The CFI works fine and will discover the proper
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* sizes.
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*/
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#ifdef CONFIG_STXSSA_4M
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#define CONFIG_SYS_FLASH_BASE 0xFFC00000 /* start of 4 MiB flash */
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#else
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#define CONFIG_SYS_FLASH_BASE 0xFC000000 /* start of 64 MiB flash */
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#endif
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#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | 0x1801) /* port size 32bit */
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#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_FLASH_BASE | 0x0FF7)
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#define CONFIG_SYS_FLASH_CFI 1
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#define CONFIG_FLASH_CFI_DRIVER 1
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#undef CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* use buffered writes (20x faster) */
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#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
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#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
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#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
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#define CONFIG_SYS_FLASH_PROTECTION
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/* The configuration latch is Chip Select 1.
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* It's an 8-bit latch in the lower 8 bits of the word.
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*/
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#define CONFIG_SYS_LBC_CFGLATCH_BASE 0xFB000000 /* Base of config latch */
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#define CONFIG_SYS_BR1_PRELIM 0xFB001801 /* 32-bit port */
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#define CONFIG_SYS_OR1_PRELIM 0xFFFF0FF7 /* 64K is enough */
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
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#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
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#define CONFIG_SYS_RAMBOOT
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#else
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#undef CONFIG_SYS_RAMBOOT
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#endif
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#ifdef CONFIG_SYS_RAMBOOT
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#define CONFIG_SYS_CCSRBAR_DEFAULT 0x40000000 /* CCSRBAR by BDI cfg */
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#endif
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#define CONFIG_SYS_CCSRBAR 0xe0000000
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#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
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/* DDR Setup */
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#define CONFIG_SYS_FSL_DDR1
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#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
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#define CONFIG_DDR_SPD
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#undef CONFIG_FSL_DDR_INTERACTIVE
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#undef CONFIG_DDR_ECC /* only for ECC DDR module */
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#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */
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#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
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#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
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#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
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#define CONFIG_NUM_DDR_CONTROLLERS 1
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#define CONFIG_DIMM_SLOTS_PER_CTLR 1
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#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
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/* I2C addresses of SPD EEPROMs */
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#define SPD_EEPROM_ADDRESS 0x54 /* CTLR 0 DIMM 0 */
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#undef CONFIG_CLOCKS_IN_MHZ
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/* local bus definitions */
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#define CONFIG_SYS_BR2_PRELIM 0xf8001861 /* 64MB localbus SDRAM */
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#define CONFIG_SYS_OR2_PRELIM 0xfc006901
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#define CONFIG_SYS_LBC_LCRR 0x00030004 /* local bus freq */
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#define CONFIG_SYS_LBC_LBCR 0x00000000
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#define CONFIG_SYS_LBC_LSRT 0x20000000
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#define CONFIG_SYS_LBC_MRTPR 0x20000000
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#define CONFIG_SYS_LBC_LSDMR_1 0x2861b723
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#define CONFIG_SYS_LBC_LSDMR_2 0x0861b723
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#define CONFIG_SYS_LBC_LSDMR_3 0x0861b723
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#define CONFIG_SYS_LBC_LSDMR_4 0x1861b723
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#define CONFIG_SYS_LBC_LSDMR_5 0x4061b723
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#define CONFIG_SYS_INIT_RAM_LOCK 1
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#define CONFIG_SYS_INIT_RAM_ADDR 0x60000000 /* Initial RAM address */
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#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
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#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
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#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
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#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
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/* Serial Port */
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#define CONFIG_CONS_INDEX 2
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#define CONFIG_SYS_NS16550
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#define CONFIG_SYS_NS16550_SERIAL
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#define CONFIG_SYS_NS16550_REG_SIZE 1
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#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
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#define CONFIG_SYS_BAUDRATE_TABLE \
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{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
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#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
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#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
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#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
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#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
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#define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */
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/* pass open firmware flat tree */
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#define CONFIG_OF_LIBFDT 1
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#define CONFIG_OF_BOARD_SETUP 1
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#define CONFIG_OF_STDOUT_VIA_ALIAS 1
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/*
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* I2C
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*/
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#define CONFIG_SYS_I2C
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#define CONFIG_SYS_I2C_FSL
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#define CONFIG_SYS_FSL_I2C_SPEED 400000
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#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
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#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
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#undef CONFIG_SYS_I2C_NOPROBES
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/* I2C RTC */
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#define CONFIG_RTC_DS1337 /* This is really a DS1339 RTC */
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#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
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/* I2C EEPROM. AT24C32, we keep our environment in here.
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*/
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#define CONFIG_SYS_I2C_EEPROM_ADDR 0x51 /* 1010001x */
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#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* =32 Bytes per write */
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20
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/*
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* Standard 8555 PCI mapping.
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* Addresses are mapped 1-1.
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*/
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#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
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#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
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#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
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#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
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#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
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#define CONFIG_SYS_PCI1_IO_SIZE 0x01000000 /* 16M */
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#define CONFIG_SYS_PCI2_MEM_BASE 0xa0000000
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#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE
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#define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000 /* 512M */
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#define CONFIG_SYS_PCI2_IO_BASE 0x00000000
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#define CONFIG_SYS_PCI2_IO_PHYS 0xe3000000
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#define CONFIG_SYS_PCI2_IO_SIZE 0x01000000 /* 16M */
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#if defined(CONFIG_PCI) /* PCI Ethernet card */
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#define CONFIG_MPC85XX_PCI2 1
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#define CONFIG_PCI_PNP /* do pci plug-and-play */
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#define CONFIG_EEPRO100
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#define CONFIG_TULIP
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#if !defined(CONFIG_PCI_PNP)
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#define PCI_ENET0_IOADDR 0xe0000000
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#define PCI_ENET0_MEMADDR 0xe0000000
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#define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
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#endif
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#define CONFIG_PCI_SCAN_SHOW
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#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
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#endif /* CONFIG_PCI */
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#if defined(CONFIG_TSEC_ENET)
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#define CONFIG_MII 1 /* MII PHY management */
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#define CONFIG_TSEC1 1
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#define CONFIG_TSEC1_NAME "TSEC0"
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#define CONFIG_TSEC2 1
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#define CONFIG_TSEC2_NAME "TSEC1"
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#define TSEC1_PHY_ADDR 2
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#define TSEC2_PHY_ADDR 4
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#define TSEC1_PHYIDX 0
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#define TSEC2_PHYIDX 0
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#define TSEC1_FLAGS TSEC_GIGABIT
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#define TSEC2_FLAGS TSEC_GIGABIT
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#define CONFIG_ETHPRIME "TSEC0"
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#elif defined(CONFIG_ETHER_ON_FCC) /* CPM FCC Ethernet */
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#define CONFIG_ETHER_ON_FCC2 /* define if ether on FCC */
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#undef CONFIG_ETHER_NONE /* define if ether on something else */
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#define CONFIG_ETHER_INDEX 2 /* which channel for ether */
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#if (CONFIG_ETHER_INDEX == 2)
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/*
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* - Rx-CLK is CLK13
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* - Tx-CLK is CLK14
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* - Select bus for bd/buffers
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* - Full duplex
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*/
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#define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
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#define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
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#define CONFIG_SYS_CPMFCR_RAMTYPE 0
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#if 0
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#define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE)
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#else
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#define CONFIG_SYS_FCC_PSMR 0
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#endif
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#define FETH2_RST 0x01
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#elif (CONFIG_ETHER_INDEX == 3)
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/* need more definitions here for FE3 */
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#define FETH3_RST 0x80
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#endif /* CONFIG_ETHER_INDEX */
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/* MDIO is done through the TSEC0 control.
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*/
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#define CONFIG_MII /* MII PHY management */
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#undef CONFIG_BITBANGMII /* bit-bang MII PHY management */
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#endif
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/* Environment - default config is in flash, see below */
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#if 0 /* in EEPROM */
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# define CONFIG_ENV_IS_IN_EEPROM 1
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# define CONFIG_ENV_OFFSET 0
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# define CONFIG_ENV_SIZE 2048
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#else /* in flash */
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# define CONFIG_ENV_IS_IN_FLASH 1
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# ifdef CONFIG_STXSSA_4M
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# define CONFIG_ENV_SECT_SIZE 0x20000
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# else /* default configuration - 64 MiB flash */
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# define CONFIG_ENV_SECT_SIZE 0x40000
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# endif
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# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
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# define CONFIG_ENV_SIZE 0x4000
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# define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE)
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# define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
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#endif
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#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
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#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
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#define CONFIG_TIMESTAMP /* Print image info with ts */
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/*
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* BOOTP options
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*/
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#define CONFIG_BOOTP_BOOTFILESIZE
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#define CONFIG_BOOTP_BOOTPATH
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#define CONFIG_BOOTP_GATEWAY
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#define CONFIG_BOOTP_HOSTNAME
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/*
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* Command line configuration.
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*/
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#include <config_cmd_default.h>
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#define CONFIG_CMD_DATE
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#define CONFIG_CMD_DHCP
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#define CONFIG_CMD_EEPROM
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#define CONFIG_CMD_I2C
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#define CONFIG_CMD_NFS
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#define CONFIG_CMD_PING
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#define CONFIG_CMD_SNTP
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#define CONFIG_CMD_REGINFO
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#if defined(CONFIG_PCI)
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#define CONFIG_CMD_PCI
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#endif
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#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
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#define CONFIG_CMD_MII
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#endif
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#if defined(CONFIG_SYS_RAMBOOT)
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#undef CONFIG_CMD_SAVEENV
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#undef CONFIG_CMD_LOADS
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#else
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#define CONFIG_CMD_ELF
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#endif
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#undef CONFIG_WATCHDOG /* watchdog disabled */
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/*
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* Miscellaneous configurable options
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*/
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#define CONFIG_SYS_LONGHELP /* undef to save memory */
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#define CONFIG_SYS_PROMPT "SSA=> " /* Monitor Command Prompt */
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#if defined(CONFIG_CMD_KGDB)
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#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
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#else
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#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
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#endif
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
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#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
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#define CONFIG_SYS_LOAD_ADDR 0x1000000 /* default load address */
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 8 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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*/
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#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
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#if defined(CONFIG_CMD_KGDB)
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#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
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#endif
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/*Note: change below for your network setting!!! */
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#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
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#define CONFIG_HAS_ETH0
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#define CONFIG_ETHADDR 00:e0:0c:07:9b:8a
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#define CONFIG_HAS_ETH1
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#define CONFIG_ETH1ADDR 00:e0:0c:07:9b:8b
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#define CONFIG_HAS_ETH2
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#define CONFIG_ETH2ADDR 00:e0:0c:07:9b:8c
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#endif
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/*
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* Environment in EEPROM is compatible with different flash sector sizes,
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* but only little space is available, so we use a very simple setup.
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* With environment in flash, we use a more powerful default configuration.
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*/
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#ifdef CONFIG_ENV_IS_IN_EEPROM /* use restricted "standard" environment */
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#define CONFIG_BAUDRATE 38400
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#define CONFIG_BOOTDELAY 3 /* -1 disable autoboot */
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#define CONFIG_BOOTCOMMAND "bootm 0xffc00000 0xffd00000"
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#define CONFIG_BOOTARGS "root=/dev/nfs rw ip=any console=ttyS1,$baudrate"
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#define CONFIG_SERVERIP 192.168.85.1
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#define CONFIG_IPADDR 192.168.85.60
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#define CONFIG_GATEWAYIP 192.168.85.1
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#define CONFIG_NETMASK 255.255.255.0
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#define CONFIG_HOSTNAME STX_SSA
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#define CONFIG_ROOTPATH "/gppproot"
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#define CONFIG_BOOTFILE "uImage"
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#define CONFIG_LOADADDR 0x1000000
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#else /* ENV IS IN FLASH -- use a full-blown envionment */
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#define CONFIG_BAUDRATE 115200
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#define CONFIG_BOOTDELAY 5 /* -1 disable autoboot */
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#define CONFIG_PREBOOT "echo;" \
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"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
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"echo"
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#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"hostname=gp3ssa\0" \
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"bootfile=/tftpboot/gp3ssa/uImage\0" \
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"loadaddr=400000\0" \
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"netdev=eth0\0" \
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"consdev=ttyS1\0" \
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"nfsargs=setenv bootargs root=/dev/nfs rw " \
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"nfsroot=$serverip:$rootpath\0" \
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"ramargs=setenv bootargs root=/dev/ram rw\0" \
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"addip=setenv bootargs $bootargs " \
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"ip=$ipaddr:$serverip:$gatewayip:$netmask" \
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":$hostname:$netdev:off panic=1\0" \
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"addcons=setenv bootargs $bootargs " \
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"console=$consdev,$baudrate\0" \
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"flash_nfs=run nfsargs addip addcons;" \
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"bootm $kernel_addr\0" \
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"flash_self=run ramargs addip addcons;" \
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"bootm $kernel_addr $ramdisk_addr\0" \
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"net_nfs=tftp $loadaddr $bootfile;" \
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"run nfsargs addip addcons;bootm\0" \
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"rootpath=/opt/eldk/ppc_85xx\0" \
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"kernel_addr=FC000000\0" \
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"ramdisk_addr=FC200000\0" \
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""
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#define CONFIG_BOOTCOMMAND "run flash_self"
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#endif /* CONFIG_ENV_IS_IN_EEPROM */
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#endif /* __CONFIG_H */
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