mirror of
https://github.com/AsahiLinux/u-boot
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29caf9305b
Globally replace all occurances of WATCHDOG_RESET() with schedule(), which handles the HW_WATCHDOG functionality and the cyclic infrastructure. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Tom Rini <trini@konsulko.com> [am335x_evm, mx6cuboxi, rpi_3,dra7xx_evm, pine64_plus, am65x_evm, j721e_evm]
246 lines
5.2 KiB
C
246 lines
5.2 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* UART driver for MediaTek MT7620 and earlier SoCs
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*
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* Copyright (C) 2020 MediaTek Inc.
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* Author: Weijie Gao <weijie.gao@mediatek.com>
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*/
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#include <clk.h>
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#include <div64.h>
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#include <dm.h>
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#include <errno.h>
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#include <log.h>
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#include <reset.h>
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#include <serial.h>
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#include <watchdog.h>
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#include <asm/io.h>
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#include <asm/types.h>
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#include <asm/addrspace.h>
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#include <dm/device_compat.h>
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#include <linux/err.h>
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#if CONFIG_IS_ENABLED(OF_PLATDATA)
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#include <dt-structs.h>
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#endif
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struct mt7620_serial_regs {
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u32 rbr;
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u32 thr;
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u32 ier;
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u32 iir;
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u32 fcr;
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u32 lcr;
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u32 mcr;
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u32 lsr;
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u32 msr;
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u32 scratch;
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u32 dl;
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u32 dll;
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u32 dlm;
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u32 ifctl;
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};
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#define UART_LCR_WLS_8 0x03 /* 8 bit character length */
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#define UART_LSR_DR 0x01 /* Data ready */
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#define UART_LSR_THRE 0x20 /* Xmit holding register empty */
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#define UART_LSR_TEMT 0x40 /* Xmitter empty */
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#define UART_MCR_DTR 0x01 /* DTR */
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#define UART_MCR_RTS 0x02 /* RTS */
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#define UART_FCR_FIFO_EN 0x01 /* Fifo enable */
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#define UART_FCR_RXSR 0x02 /* Receiver soft reset */
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#define UART_FCR_TXSR 0x04 /* Transmitter soft reset */
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#define UART_MCRVAL (UART_MCR_DTR | \
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UART_MCR_RTS)
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/* Clear & enable FIFOs */
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#define UART_FCRVAL (UART_FCR_FIFO_EN | \
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UART_FCR_RXSR | \
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UART_FCR_TXSR)
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struct mt7620_serial_plat {
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#if CONFIG_IS_ENABLED(OF_PLATDATA)
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struct dtd_serial_mt7620 dtplat;
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#endif
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struct mt7620_serial_regs __iomem *regs;
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u32 clock;
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};
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static void _mt7620_serial_setbrg(struct mt7620_serial_plat *plat, int baud)
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{
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u32 quot;
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/* set divisor */
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quot = DIV_ROUND_CLOSEST(plat->clock, 16 * baud);
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writel(quot, &plat->regs->dl);
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/* set character length and stop bits */
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writel(UART_LCR_WLS_8, &plat->regs->lcr);
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}
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static int mt7620_serial_setbrg(struct udevice *dev, int baudrate)
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{
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struct mt7620_serial_plat *plat = dev_get_plat(dev);
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_mt7620_serial_setbrg(plat, baudrate);
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return 0;
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}
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static int mt7620_serial_putc(struct udevice *dev, const char ch)
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{
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struct mt7620_serial_plat *plat = dev_get_plat(dev);
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if (!(readl(&plat->regs->lsr) & UART_LSR_THRE))
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return -EAGAIN;
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writel(ch, &plat->regs->thr);
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if (ch == '\n')
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schedule();
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return 0;
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}
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static int mt7620_serial_getc(struct udevice *dev)
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{
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struct mt7620_serial_plat *plat = dev_get_plat(dev);
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if (!(readl(&plat->regs->lsr) & UART_LSR_DR))
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return -EAGAIN;
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return readl(&plat->regs->rbr);
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}
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static int mt7620_serial_pending(struct udevice *dev, bool input)
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{
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struct mt7620_serial_plat *plat = dev_get_plat(dev);
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if (input)
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return (readl(&plat->regs->lsr) & UART_LSR_DR) ? 1 : 0;
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return (readl(&plat->regs->lsr) & UART_LSR_THRE) ? 0 : 1;
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}
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static int mt7620_serial_probe(struct udevice *dev)
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{
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struct mt7620_serial_plat *plat = dev_get_plat(dev);
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#if CONFIG_IS_ENABLED(OF_PLATDATA)
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plat->regs = (void __iomem *)KSEG1ADDR(plat->dtplat.reg[0]);
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plat->clock = plat->dtplat.clock_frequency;
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#endif
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/* Disable interrupt */
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writel(0, &plat->regs->ier);
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writel(UART_MCRVAL, &plat->regs->mcr);
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writel(UART_FCRVAL, &plat->regs->fcr);
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return 0;
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}
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#if CONFIG_IS_ENABLED(OF_REAL)
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static int mt7620_serial_of_to_plat(struct udevice *dev)
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{
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struct mt7620_serial_plat *plat = dev_get_plat(dev);
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struct reset_ctl reset_uart;
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struct clk clk;
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int err;
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err = reset_get_by_index(dev, 0, &reset_uart);
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if (!err)
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reset_deassert(&reset_uart);
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plat->regs = dev_remap_addr_index(dev, 0);
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if (!plat->regs) {
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dev_err(dev, "mt7620_serial: unable to map UART registers\n");
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return -EINVAL;
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}
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err = clk_get_by_index(dev, 0, &clk);
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if (!err) {
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err = clk_get_rate(&clk);
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if (!IS_ERR_VALUE(err))
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plat->clock = err;
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} else if (err != -ENOENT && err != -ENODEV && err != -ENOSYS) {
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dev_err(dev, "mt7620_serial: failed to get clock\n");
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return err;
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}
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if (!plat->clock)
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plat->clock = dev_read_u32_default(dev, "clock-frequency", 0);
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if (!plat->clock) {
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dev_err(dev, "mt7620_serial: clock not defined\n");
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return -EINVAL;
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}
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return 0;
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}
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static const struct udevice_id mt7620_serial_ids[] = {
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{ .compatible = "mediatek,mt7620-uart" },
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{ }
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};
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#endif
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static const struct dm_serial_ops mt7620_serial_ops = {
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.putc = mt7620_serial_putc,
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.pending = mt7620_serial_pending,
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.getc = mt7620_serial_getc,
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.setbrg = mt7620_serial_setbrg,
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};
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U_BOOT_DRIVER(serial_mt7620) = {
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.name = "serial_mt7620",
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.id = UCLASS_SERIAL,
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#if CONFIG_IS_ENABLED(OF_REAL)
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.of_match = mt7620_serial_ids,
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.of_to_plat = mt7620_serial_of_to_plat,
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#endif
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.plat_auto = sizeof(struct mt7620_serial_plat),
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.probe = mt7620_serial_probe,
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.ops = &mt7620_serial_ops,
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.flags = DM_FLAG_PRE_RELOC,
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};
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DM_DRIVER_ALIAS(serial_mt7620, mediatek_mt7620_uart);
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#ifdef CONFIG_DEBUG_UART_MT7620
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#include <debug_uart.h>
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static inline void _debug_uart_init(void)
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{
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struct mt7620_serial_plat plat;
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plat.regs = (void *)CONFIG_VAL(DEBUG_UART_BASE);
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plat.clock = CONFIG_DEBUG_UART_CLOCK;
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writel(0, &plat.regs->ier);
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writel(UART_MCRVAL, &plat.regs->mcr);
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writel(UART_FCRVAL, &plat.regs->fcr);
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_mt7620_serial_setbrg(&plat, CONFIG_BAUDRATE);
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}
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static inline void _debug_uart_putc(int ch)
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{
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struct mt7620_serial_regs __iomem *regs =
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(void *)CONFIG_VAL(DEBUG_UART_BASE);
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while (!(readl(®s->lsr) & UART_LSR_THRE))
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;
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writel(ch, ®s->thr);
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}
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DEBUG_UART_FUNCS
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#endif
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