mirror of
https://github.com/AsahiLinux/u-boot
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81fb00b884
J721S2 can support two instances for DDR. Therefore, add the device support for the same and use 4266MT/s as DDR frequency. Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
198 lines
5 KiB
Text
198 lines
5 KiB
Text
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
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*/
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/dts-v1/;
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#include "k3-j721s2-som-p0.dtsi"
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#include "k3-j721s2-ddr-evm-lp4-4266.dtsi"
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#include "k3-j721s2-ddr.dtsi"
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/ {
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chosen {
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firmware-loader = &fs_loader0;
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stdout-path = &main_uart8;
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tick-timer = &timer1;
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};
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aliases {
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remoteproc0 = &sysctrler;
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remoteproc1 = &a72_0;
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};
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fs_loader0: fs_loader@0 {
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compatible = "u-boot,fs-loader";
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u-boot,dm-pre-reloc;
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};
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a72_0: a72@0 {
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compatible = "ti,am654-rproc";
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reg = <0x0 0x00a90000 0x0 0x10>;
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power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
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<&k3_pds 202 TI_SCI_PD_EXCLUSIVE>;
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resets = <&k3_reset 202 0>;
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clocks = <&k3_clks 61 1>;
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assigned-clocks = <&k3_clks 61 1>, <&k3_clks 202 0>;
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assigned-clock-parents = <&k3_clks 61 2>;
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assigned-clock-rates = <200000000>, <2000000000>;
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ti,sci = <&sms>;
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ti,sci-proc-id = <32>;
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ti,sci-host-id = <10>;
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u-boot,dm-spl;
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};
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clk_200mhz: dummy_clock_200mhz {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <200000000>;
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u-boot,dm-spl;
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};
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clk_19_2mhz: dummy_clock_19_2mhz {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <19200000>;
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u-boot,dm-spl;
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};
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};
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&cbass_mcu_wakeup {
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sa3_secproxy: secproxy@44880000 {
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u-boot,dm-spl;
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compatible = "ti,am654-secure-proxy";
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reg = <0x0 0x44880000 0x0 0x20000>,
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<0x0 0x44860000 0x0 0x20000>,
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<0x0 0x43600000 0x0 0x10000>;
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reg-names = "rt", "scfg", "target_data";
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#mbox-cells = <1>;
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};
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mcu_secproxy: secproxy@2a380000 {
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compatible = "ti,am654-secure-proxy";
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reg = <0x0 0x2a380000 0x0 0x80000>,
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<0x0 0x2a400000 0x0 0x80000>,
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<0x0 0x2a480000 0x0 0x80000>;
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reg-names = "rt", "scfg", "target_data";
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#mbox-cells = <1>;
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u-boot,dm-spl;
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};
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sysctrler: sysctrler {
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compatible = "ti,am654-system-controller";
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mboxes= <&mcu_secproxy 4>, <&mcu_secproxy 5>, <&sa3_secproxy 5>;
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mbox-names = "tx", "rx", "boot_notify";
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u-boot,dm-spl;
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};
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dm_tifs: dm-tifs {
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compatible = "ti,j721e-dm-sci";
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ti,host-id = <3>;
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ti,secure-host;
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mbox-names = "rx", "tx";
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mboxes= <&mcu_secproxy 21>,
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<&mcu_secproxy 23>;
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u-boot,dm-spl;
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};
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};
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&main_pmx0 {
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main_uart8_pins_default: main-uart8-pins-default {
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pinctrl-single,pins = <
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J721S2_IOPAD(0x040, PIN_INPUT, 14) /* (AC28) MCASP0_AXR0.UART8_CTSn */
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J721S2_IOPAD(0x044, PIN_OUTPUT, 14) /* (Y26) MCASP0_AXR1.UART8_RTSn */
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J721S2_IOPAD(0x0d0, PIN_INPUT, 11) /* (AF26) SPI0_CS1.UART8_RXD */
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J721S2_IOPAD(0x0d4, PIN_OUTPUT, 11) /* (AH27) SPI0_CLK.UART8_TXD */
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>;
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};
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main_mmc1_pins_default: main-mmc1-pins-default {
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pinctrl-single,pins = <
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J721S2_IOPAD(0x104, PIN_INPUT, 0) /* (P23) MMC1_CLK */
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J721S2_IOPAD(0x108, PIN_INPUT, 0) /* (N24) MMC1_CMD */
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J721S2_IOPAD(0x100, PIN_INPUT, 0) /* (###) MMC1_CLKLB */
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J721S2_IOPAD(0x0fc, PIN_INPUT, 0) /* (M23) MMC1_DAT0 */
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J721S2_IOPAD(0x0f8, PIN_INPUT, 0) /* (P24) MMC1_DAT1 */
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J721S2_IOPAD(0x0f4, PIN_INPUT, 0) /* (R24) MMC1_DAT2 */
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J721S2_IOPAD(0x0f0, PIN_INPUT, 0) /* (R22) MMC1_DAT3 */
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J721S2_IOPAD(0x0e8, PIN_INPUT, 8) /* (AE25) TIMER_IO0.MMC1_SDCD */
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>;
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};
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};
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&wkup_pmx0 {
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mcu_uart0_pins_default: mcu-uart0-pins-default {
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u-boot,dm-spl;
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pinctrl-single,pins = <
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J721S2_WKUP_IOPAD(0x0f8, PIN_INPUT, 0) /* (B24) WKUP_GPIO0_14.MCU_UART0_CTSn */
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J721S2_WKUP_IOPAD(0x0fc, PIN_OUTPUT, 0) /* (D25) WKUP_GPIO0_15.MCU_UART0_RTSn */
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J721S2_WKUP_IOPAD(0x0f4, PIN_INPUT, 0) /* (C24) WKUP_GPIO0_13.MCU_UART0_RXD */
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J721S2_WKUP_IOPAD(0x0f0, PIN_OUTPUT, 0) /* (C25) WKUP_GPIO0_12.MCU_UART0_TXD */
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>;
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};
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wkup_uart0_pins_default: wkup-uart0-pins-default {
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u-boot,dm-spl;
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pinctrl-single,pins = <
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J721S2_WKUP_IOPAD(0x0d8, PIN_INPUT, 0) /* (E25) WKUP_GPIO0_6.WKUP_UART0_CTSn */
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J721S2_WKUP_IOPAD(0x0dc, PIN_OUTPUT, 0) /* (F28) WKUP_GPIO0_7.WKUP_UART0_RTSn */
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J721S2_WKUP_IOPAD(0x0b0, PIN_INPUT, 0) /* (D28) WKUP_UART0_RXD */
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J721S2_WKUP_IOPAD(0x0b4, PIN_OUTPUT, 0) /* (D27) WKUP_UART0_TXD */
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>;
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};
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};
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&sms {
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mboxes= <&mcu_secproxy 8>, <&mcu_secproxy 6>, <&mcu_secproxy 5>;
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mbox-names = "tx", "rx", "notify";
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ti,host-id = <4>;
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ti,secure-host;
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u-boot,dm-spl;
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};
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&wkup_uart0 {
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pinctrl-names = "default";
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pinctrl-0 = <&wkup_uart0_pins_default>;
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};
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&mcu_uart0 {
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pinctrl-names = "default";
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pinctrl-0 = <&mcu_uart0_pins_default>;
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};
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&main_uart8 {
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pinctrl-names = "default";
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pinctrl-0 = <&main_uart8_pins_default>;
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};
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&main_sdhci0 {
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/delete-property/ power-domains;
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/delete-property/ assigned-clocks;
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/delete-property/ assigned-clock-parents;
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clock-names = "clk_xin";
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clocks = <&clk_200mhz>;
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ti,driver-strength-ohm = <50>;
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non-removable;
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bus-width = <8>;
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};
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&main_sdhci1 {
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/delete-property/ power-domains;
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/delete-property/ assigned-clocks;
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/delete-property/ assigned-clock-parents;
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pinctrl-0 = <&main_mmc1_pins_default>;
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pinctrl-names = "default";
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clock-names = "clk_xin";
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clocks = <&clk_200mhz>;
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ti,driver-strength-ohm = <50>;
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};
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&mcu_ringacc {
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ti,sci = <&dm_tifs>;
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};
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&mcu_udmap {
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ti,sci = <&dm_tifs>;
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};
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#include "k3-j721s2-common-proc-board-u-boot.dtsi"
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