mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-09-22 23:52:03 +00:00
4fb2536e5b
Move MTRR-listing code into a common file so it can be used from SPL. Update the 'mtrr' command to call it. Use this in SPL just before adjusting the MTRRs, so we can see the state set up by the board. Only show it when debug is enabled. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
225 lines
5.9 KiB
C
225 lines
5.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (c) 2014 Google, Inc
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*
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* From Coreboot file of the same name
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*/
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#ifndef _ASM_MTRR_H
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#define _ASM_MTRR_H
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/* MTRR region types */
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#define MTRR_TYPE_UNCACHEABLE 0
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#define MTRR_TYPE_WRCOMB 1
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#define MTRR_TYPE_WRTHROUGH 4
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#define MTRR_TYPE_WRPROT 5
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#define MTRR_TYPE_WRBACK 6
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#define MTRR_TYPE_COUNT 7
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#define MTRR_CAP_MSR 0x0fe
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#define MTRR_DEF_TYPE_MSR 0x2ff
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#define MTRR_CAP_SMRR (1 << 11)
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#define MTRR_CAP_WC (1 << 10)
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#define MTRR_CAP_FIX (1 << 8)
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#define MTRR_CAP_VCNT_MASK 0xff
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#define MTRR_DEF_TYPE_MASK 0xff
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#define MTRR_DEF_TYPE_EN (1 << 11)
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#define MTRR_DEF_TYPE_FIX_EN (1 << 10)
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#define MTRR_PHYS_BASE_MSR(reg) (0x200 + 2 * (reg))
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#define MTRR_PHYS_MASK_MSR(reg) (0x200 + 2 * (reg) + 1)
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#define MTRR_PHYS_MASK_VALID (1 << 11)
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#define MTRR_BASE_TYPE_MASK 0x7
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/* Maximum number of MTRRs supported - see also mtrr_get_var_count() */
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#define MTRR_MAX_COUNT 10
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#define NUM_FIXED_MTRRS 11
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#define RANGES_PER_FIXED_MTRR 8
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#define NUM_FIXED_RANGES (NUM_FIXED_MTRRS * RANGES_PER_FIXED_MTRR)
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#define MTRR_FIX_64K_00000_MSR 0x250
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#define MTRR_FIX_16K_80000_MSR 0x258
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#define MTRR_FIX_16K_A0000_MSR 0x259
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#define MTRR_FIX_4K_C0000_MSR 0x268
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#define MTRR_FIX_4K_C8000_MSR 0x269
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#define MTRR_FIX_4K_D0000_MSR 0x26a
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#define MTRR_FIX_4K_D8000_MSR 0x26b
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#define MTRR_FIX_4K_E0000_MSR 0x26c
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#define MTRR_FIX_4K_E8000_MSR 0x26d
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#define MTRR_FIX_4K_F0000_MSR 0x26e
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#define MTRR_FIX_4K_F8000_MSR 0x26f
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#define MTRR_FIX_TYPE(t) ((t << 24) | (t << 16) | (t << 8) | t)
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#if !defined(__ASSEMBLY__)
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/**
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* Information about the previous MTRR state, set up by mtrr_open()
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*
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* @deftype: Previous value of MTRR_DEF_TYPE_MSR
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* @enable_cache: true if cache was enabled
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*/
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struct mtrr_state {
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uint64_t deftype;
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bool enable_cache;
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};
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/**
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* struct mtrr - Information about a single MTRR
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*
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* @base: Base address and MTRR_BASE_TYPE_MASK
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* @mask: Mask and MTRR_PHYS_MASK_VALID
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*/
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struct mtrr {
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u64 base;
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u64 mask;
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};
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/**
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* struct mtrr_info - Information about all MTRRs
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*
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* @mtrr: Information about each mtrr
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*/
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struct mtrr_info {
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struct mtrr mtrr[MTRR_MAX_COUNT];
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};
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/**
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* mtrr_open() - Prepare to adjust MTRRs
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*
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* Use mtrr_open() passing in a structure - this function will init it. Then
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* when done, pass the same structure to mtrr_close() to re-enable MTRRs and
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* possibly the cache.
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*
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* @state: Empty structure to pass in to hold settings
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* @do_caches: true to disable caches before opening
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*/
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void mtrr_open(struct mtrr_state *state, bool do_caches);
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/**
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* mtrr_close() - Clean up after adjusting MTRRs, and enable them
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*
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* This uses the structure containing information returned from mtrr_open().
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*
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* @state: Structure from mtrr_open()
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* @state: true to restore cache state to that before mtrr_open()
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*/
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void mtrr_close(struct mtrr_state *state, bool do_caches);
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/**
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* mtrr_add_request() - Add a new MTRR request
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*
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* This adds a request for a memory region to be set up in a particular way.
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*
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* @type: Requested type (MTRR_TYPE_)
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* @start: Start address
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* @size: Size, must be power of 2
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*
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* @return: 0 on success, non-zero on failure
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*/
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int mtrr_add_request(int type, uint64_t start, uint64_t size);
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/**
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* mtrr_commit() - set up the MTRR registers based on current requests
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*
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* This sets up MTRRs for the available DRAM and the requests received so far.
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* It must be called with caches disabled.
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*
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* @do_caches: true if caches are currently on
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*
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* @return: 0 on success, non-zero on failure
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*/
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int mtrr_commit(bool do_caches);
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/**
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* mtrr_set_next_var() - set up a variable MTRR
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*
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* This finds the first free variable MTRR and sets to the given area
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*
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* @type: Requested type (MTRR_TYPE_)
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* @start: Start address
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* @size: Size, must be power of 2
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* Return: 0 on success, -EINVAL if size is not power of 2,
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* -ENOSPC if there are no more MTRRs
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*/
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int mtrr_set_next_var(uint type, uint64_t base, uint64_t size);
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/**
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* mtrr_read_all() - Save all the MTRRs
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*
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* This reads all MTRRs from the boot CPU into a struct so they can be loaded
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* onto other CPUs
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*
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* @info: Place to put the MTRR info
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*/
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void mtrr_read_all(struct mtrr_info *info);
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/**
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* mtrr_set_valid() - Set the valid flag for a selected MTRR and CPU(s)
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*
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* @cpu_select: Selected CPUs (either a CPU number or MP_SELECT_...)
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* @reg: MTRR register to write (0-7)
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* @valid: Valid flag to write
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* Return: 0 on success, -ve on error
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*/
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int mtrr_set_valid(int cpu_select, int reg, bool valid);
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/**
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* mtrr_set() - Set the base address and mask for a selected MTRR and CPU(s)
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*
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* @cpu_select: Selected CPUs (either a CPU number or MP_SELECT_...)
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* @reg: MTRR register to write (0-7)
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* @base: Base address and MTRR_BASE_TYPE_MASK
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* @mask: Mask and MTRR_PHYS_MASK_VALID
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* Return: 0 on success, -ve on error
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*/
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int mtrr_set(int cpu_select, int reg, u64 base, u64 mask);
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/**
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* mtrr_get_var_count() - Get the number of variable MTRRs
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*
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* Some CPUs have more than 8 MTRRs. This function returns the actual number
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*
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* Return: number of variable MTRRs
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*/
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int mtrr_get_var_count(void);
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/**
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* mtrr_list() - List the MTRRs
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*
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* Shows a list of all the MTRRs including their values
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*
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* @reg_count: Number of registers to show. You can use mtrr_get_var_count() for
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* this
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* @cpu_select: CPU to use. Use MP_SELECT_BSP for the boot CPU
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* Returns: 0 if OK, -ve if the CPU was not found
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*/
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int mtrr_list(int reg_count, int cpu_select);
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/**
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* mtrr_get_type_by_name() - Get the type of an MTRR given its type name
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*
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* @typename: Name to check
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* Returns: MTRR type (MTRR_TYPE_...) or -EINVAL if invalid
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*/
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int mtrr_get_type_by_name(const char *typename);
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#endif
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#if ((CONFIG_XIP_ROM_SIZE & (CONFIG_XIP_ROM_SIZE - 1)) != 0)
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# error "CONFIG_XIP_ROM_SIZE is not a power of 2"
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#endif
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#if ((CONFIG_CACHE_ROM_SIZE & (CONFIG_CACHE_ROM_SIZE - 1)) != 0)
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# error "CONFIG_CACHE_ROM_SIZE is not a power of 2"
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#endif
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#define CACHE_ROM_BASE (((1 << 20) - (CONFIG_CACHE_ROM_SIZE >> 12)) << 12)
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#endif
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