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https://github.com/AsahiLinux/u-boot
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978a8a296e
This enum is currently anonymous. Add a name so it can be used in the code. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
122 lines
3.4 KiB
C
122 lines
3.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2019 Intel Corporation.
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*
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* Taken from coreboot intelblocks/nvs.h
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* Copyright 2019 Google LLC
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*/
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#ifndef _INTEL_GNVS_H_
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#define _INTEL_GNVS_H_
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#include <linux/bitops.h>
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/*
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* The chromeos_acpi portion of ACPI GNVS is assumed to live from offset
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* 0x100 - 0x1000. When defining acpi_global_nvs, use check_member
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* to ensure that it is properly aligned:
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*
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* check_member(acpi_global_nvs, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
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*/
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#define GNVS_CHROMEOS_ACPI_OFFSET 0x100
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enum {
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BOOT_REASON_OTHER = 0,
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BOOT_REASON_S3DIAG = 9
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};
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enum {
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CHSW_RECOVERY_X86 = BIT(1),
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CHSW_RECOVERY_EC = BIT(2),
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CHSW_DEVELOPER_SWITCH = BIT(5),
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CHSW_FIRMWARE_WP = BIT(9),
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};
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enum {
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RECOVERY_REASON_NONE = 0,
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RECOVERY_REASON_ME = 1
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};
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enum {
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ACTIVE_ECFW_RO = 0,
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ACTIVE_ECFW_RW = 1
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};
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enum {
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BINF_RECOVERY = 0,
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BINF_RW_A = 1,
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BINF_RW_B = 2
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};
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/**
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* enum cros_fw_type_t - Used to indicate Chromium OS firmware type
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*
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* Chromium OS uses a region of the GNVS starting at offset 0x100 to store
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* various bits of information, including the type of firmware being booted
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*/
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enum cros_fw_type_t {
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FIRMWARE_TYPE_AUTO_DETECT = -1,
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FIRMWARE_TYPE_RECOVERY = 0,
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FIRMWARE_TYPE_NORMAL = 1,
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FIRMWARE_TYPE_DEVELOPER = 2,
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FIRMWARE_TYPE_NETBOOT = 3,
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FIRMWARE_TYPE_LEGACY = 4,
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};
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struct __packed chromeos_acpi_gnvs {
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/* ChromeOS-specific */
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u32 boot_reason; /* 00 boot reason */
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u32 active_main_fw; /* 04 (0=recovery, 1=A, 2=B) */
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u32 activeec_fw; /* 08 (0=RO, 1=RW) */
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u16 switches; /* 0c CHSW */
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u8 hwid[256]; /* 0e HWID */
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u8 fwid[64]; /* 10e FWID */
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u8 frid[64]; /* 14e FRID - 275 */
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u32 main_fw_type; /* 18e (2 = developer mode) */
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u32 recovery_reason; /* 192 recovery reason */
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u32 fmap_base; /* 196 fmap base address */
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u8 vdat[3072]; /* 19a VDAT space filled by verified boot */
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u32 fwid_ptr; /* d9a smbios bios version */
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u32 mehh[8]; /* d9e management engine hash */
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u32 ramoops_base; /* dbe ramoops base address */
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u32 ramoops_len; /* dc2 ramoops length */
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u32 vpd_ro_base; /* dc6 pointer to RO_VPD */
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u32 vpd_ro_size; /* dca size of RO_VPD */
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u32 vpd_rw_base; /* dce pointer to RW_VPD */
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u32 vpd_rw_size; /* dd2 size of RW_VPD */
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u8 pad[298]; /* dd6-eff */
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};
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struct __packed acpi_global_nvs {
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/* Miscellaneous */
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u8 pcnt; /* 0x00 - Processor Count */
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u8 ppcm; /* 0x01 - Max PPC State */
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u8 lids; /* 0x02 - LID State */
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u8 pwrs; /* 0x03 - AC Power State */
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u8 dpte; /* 0x04 - Enable DPTF */
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u32 cbmc; /* 0x05 - 0x08 - coreboot Memory Console */
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u64 pm1i; /* 0x09 - 0x10 - System Wake Source - PM1 Index */
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u64 gpei; /* 0x11 - 0x18 - GPE Wake Source */
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u64 nhla; /* 0x19 - 0x20 - NHLT Address */
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u32 nhll; /* 0x21 - 0x24 - NHLT Length */
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u32 prt0; /* 0x25 - 0x28 - PERST_0 Address */
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u8 scdp; /* 0x29 - SD_CD GPIO portid */
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u8 scdo; /* 0x2a - GPIO pad offset relative to the community */
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u8 uior; /* 0x2b - UART debug controller init on S3 resume */
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u8 ecps; /* 0x2c - SGX Enabled status */
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u64 emna; /* 0x2d - 0x34 EPC base address */
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u64 elng; /* 0x35 - 0x3C EPC Length */
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u8 unused1[0x100 - 0x3d]; /* Pad out to 256 bytes */
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#ifdef CONFIG_CHROMEOS
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/* ChromeOS-specific (0x100 - 0xfff) */
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struct chromeos_acpi_gnvs chromeos;
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#else
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u8 unused2[0x1000 - 0x100]; /* Pad out to 4096 bytes */
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#endif
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};
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#ifdef CONFIG_CHROMEOS
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check_member(acpi_global_nvs, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
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#else
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check_member(acpi_global_nvs, unused2, GNVS_CHROMEOS_ACPI_OFFSET);
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#endif
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#endif /* _INTEL_GNVS_H_ */
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